公开(公告)号：US20190267674A1

公开(公告)日：2019-08-29

申请号：US16282455

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmi CHEONG ,  Jonghwa KIM ,  Younghoon LEE ,  Daehyuk CHIN

IPC: H01M10/0587 ,  H01M10/04 ,  H01M2/02 ,  H04M1/02

Abstract: In one embodiment of the disclosure an electronic device comprising: a display; a first plate having opposing first and second faces, wherein the display is disposed on the first face; a second plate coupled to the second face of the first plate, at least one adhesive layer including a first adhesive layer adhering to the second face of the first plate, a jelly-roll, a roll fixing tape disposed on one region of the jelly-roll, a pouch containing the jelly-roll and the roll fixing tape, wherein the at least one adhesive layer including the first adhesive layer is disposed between and attached to one face of the pouch, and wherein one end of the first adhesive layer and one end of the roll fixing tape face are in the same direction while the first adhesive layer and the roll fixing tape vertically surround the one face of the pouch.

公开(公告)号：US20240427405A1

公开(公告)日：2024-12-26

申请号：US18749071

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo LEE ,  Sooyong KIM ,  Younghoon LEE ,  Jongjin LEE ,  Junho HUH

IPC: G06F1/324

Abstract: A Dynamic Voltage and Frequency Scaling (DVFS) controller, an integrated circuit including DVFS, and a method of operating the DVFS controller are provided. The integrated circuit includes at least one subblock circuit configured to process an instruction, and a DVFS controller configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage and an operating frequency, respectively, based on a resonance frequency calculated from a frequency response resulting from dynamic characteristics of an entire power system including the PMU, a power delivery network (PDN), and the subblock circuit.

公开(公告)号：US20230239388A1

公开(公告)日：2023-07-27

申请号：US18182057

申请日：2023-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulhwan LEE ,  Sunghun KIM ,  Woonbae KIM ,  Younghoon LEE ,  Hyunggeun LEE ,  Hyungseok LIM ,  Jaewon YU ,  Howon LEE ,  Sungkyu HWANG

IPC: H04M1/18 ,  H04M1/02 ,  H05K1/18

CPC classification number: H04M1/185 ,  H04M1/0266 ,  H04M1/0277 ,  H05K1/189 ,  H05K2201/10128

Abstract: An electronic device is provided. The electronic device includes a housing and a display including a transparent plate forming a front of the electronic device, a display panel viewable from the front of the electronic device through the transparent plate, a panel flexible circuit film arranged under the rear surface of the display panel including a bending part that extends toward the front surface of the display panel in a region adjacent to a first side surface of the electronic device, the bending part being electrically connected to the display panel on the front surface of the display panel, and a first support member arranged between the rear surface of the display panel and the panel flexible circuit film, a partial region of the first support member having an area larger than that of the panel flexible circuit film within a designated distance from the first side surface.

公开(公告)号：US20220155807A1

公开(公告)日：2022-05-19

申请号：US17665907

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik SEOK ,  Younghoon LEE ,  Kyungrae KIM ,  Kyungsoo LEE ,  Junho HUH

IPC: G05F1/56 ,  G06F1/26

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.

公开(公告)号：US20190214610A1

公开(公告)日：2019-07-11

申请号：US16226841

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghoon LEE ,  Jonghwa KIM ,  Hyunmi CHEONG ,  Daehyuk CHIN

IPC: H01M2/02 ,  H01M2/26 ,  H01M2/08 ,  H01M10/0587 ,  H01M10/04

CPC classification number: H01M2/0287 ,  H01M2/08 ,  H01M2/263 ,  H01M10/045 ,  H01M10/0587 ,  H01M2220/30

Abstract: An electronic device and battery included therein are disclosed. The device includes a battery which itself comprises a jelly-roll structure having a rolled stack of a cathode, a separator, and an anode; an outer cover layer enclosing surfaces of the jelly-roll; and a pouch sealing the jelly-roll and the outer cover layer. The jelly-roll includes a first surface, a second surface disposed in a opposite direction, a third surface corresponding to one side of the rolled stack and connecting the first surface and the second surface, and a fourth surface corresponding to other side of the rolled stack, connecting the first surface and the second surface, and disposed in a direction opposite to the third surface. The outer cover layer includes a first portion, a second portion, a third portion, and a fourth portion bonded to first, second, third and fourth surfaces, respectively.

公开(公告)号：US20210271276A1

公开(公告)日：2021-09-02

申请号：US17027946

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik SEOK ,  Younghoon LEE ,  Kyungrae KIM ,  Kyungsoo LEE ,  Junho HUH

IPC: G05F1/56

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.

公开(公告)号：US20140108835A1

公开(公告)日：2014-04-17

申请号：US14050793

申请日：2013-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong PARK ,  Jekook KIM ,  Chan-Woo PARK ,  Younghoon LEE

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/26 ,  G06F9/4401

Abstract: A power management integrated circuit includes a nonvolatile memory configured to store code data for driving the power management integrated circuit; a processor configured to execute program data stored at a volatile memory; and a decompression logic separated from the processor, the decompression logic being formed of hardware, configured to decompress the code data to generate program data, and configured to store the program data at the volatile memory.

Abstract translation: 电源管理集成电路包括非易失性存储器，被配置为存储用于驱动电源管理集成电路的代码数据; 处理器，被配置为执行存储在易失性存储器的程序数据; 以及与处理器分离的解压缩逻辑，所述解压缩逻辑由硬件形成，被配置为解压缩所述代码数据以生成程序数据，并且被配置为将所述程序数据存储在所述易失性存储器。