公开(公告)号：US09886379B2

公开(公告)日：2018-02-06

申请号：US14668015

申请日：2015-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjin Kim ,  Kitae Park ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Youngjin Jeon

IPC: G06F12/02 ,  G11C16/10 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F13/1673 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/1072 ,  G11C16/102

Abstract: A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor.

公开(公告)号：US09601171B2

公开(公告)日：2017-03-21

申请号：US14665148

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjin Kim ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Youngjin Jeon

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C16/06 ,  G11C16/32

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C16/06 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller.

公开(公告)号：US20140185389A1

公开(公告)日：2014-07-03

申请号：US14143154

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC: G11C7/10

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。

公开(公告)号：US09263105B2

公开(公告)日：2016-02-16

申请号：US14143154

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/04

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。