Method and apparatus of searching for operator network in a multi-radio access technology environment
    2.
    发明授权
    Method and apparatus of searching for operator network in a multi-radio access technology environment 有权
    在多无线电接入技术环境中搜索运营商网络的方法和装置

    公开(公告)号:US09008656B2

    公开(公告)日:2015-04-14

    申请号:US13951890

    申请日:2013-07-26

    CPC classification number: H04W48/16

    Abstract: A method and apparatus of searching for an operator network in a multi-Radio Access Technology (RAT) environment are provided. The method, calculating a length of a sleep interval to perform background Public Land Mobile Network (PLMN) searching, comparing the length of the sleep interval with a predetermined reference parameter, if the length of the sleep interval is larger than the reference parameter, performing background PLMN searching of a passive RAT during the sleep interval, and if the length of the sleep interval is equal to or smaller than the reference parameter, performing background PLMN searching of an active RAT during the sleep interval.

    Abstract translation: 提供了一种在多无线电接入技术(RAT)环境中搜索运营商网络的方法和装置。 该方法,如果睡眠间隔的长度大于参考参数,则计算休眠间隔的长度以执行背景公共陆地移动网络(PLMN)搜索,将睡眠间隔的长度与预定参考参数进行比较,执行 在休眠间隔期间的无源RAT的背景PLMN搜索,并且如果睡眠间隔的长度等于或小于参考参数,则在睡眠间隔期间执行活动RAT的背景PLMN搜索。

    Method of forming semiconductor device having self-aligned plug
    3.
    发明授权
    Method of forming semiconductor device having self-aligned plug 有权
    形成具有自对准插头的半导体器件的方法

    公开(公告)号:US08790976B2

    公开(公告)日:2014-07-29

    申请号:US13942149

    申请日:2013-07-15

    CPC classification number: H01L45/1683 H01L27/2463 H01L45/06

    Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

    Abstract translation: 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。

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