公开(公告)号：US20230078373A1

公开(公告)日：2023-03-16

申请号：US17989085

申请日：2022-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

公开(公告)号：US20190037645A1

公开(公告)日：2019-01-31

申请号：US15868451

申请日：2018-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Changsoo LEE

IPC: H05B3/14 ,  H05B3/26 ,  H01C17/06 ,  H01C17/30 ,  C03C3/064 ,  C03C4/16

CPC classification number: H05B3/141 ,  C03C3/064 ,  C03C4/16 ,  H01C17/06 ,  H01C17/30 ,  H05B3/262

Abstract: A The heating element structure includes: a conductive metal substrate; a heating layer spaced apart from the conductive metal substrate and configured to generate heat in response to an electrical signal; electrodes in contact with the heating layer and configured to provide the electrical signal to the heating layer; and a first insulating layer on the conductive metal substrate, the first insulating layer comprising a first matrix material and a particle, wherein a difference between a coefficient of thermal expansion (CTE) of the first matrix material and a coefficient of thermal expansion of the particle is about 4×10−6 per Kelvin or less.

公开(公告)号：US20180077755A1

公开(公告)日：2018-03-15

申请号：US15680830

申请日：2017-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seyun KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Jinhong KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Hiesang SOHN ,  Changsoo LEE

IPC: H05B3/12 ,  H05B3/14 ,  H05B3/26

CPC classification number: H05B3/12 ,  H05B3/141 ,  H05B3/146 ,  H05B3/148 ,  H05B3/26 ,  H05B3/262 ,  H05B3/265 ,  H05B2203/013 ,  H05B2203/017 ,  H05B2214/04

Abstract: A heating element includes a matrix; and a plurality of conductive fillers, wherein some of the plurality of conductive fillers include first nano-sheets and first metal media configured to reduce a contact resistance between the first nano-sheets.

公开(公告)号：US20210202833A1

公开(公告)日：2021-07-01

申请号：US16875119

申请日：2020-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: H01L45/00 ,  H01L27/24

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

公开(公告)号：US20210153300A1

公开(公告)日：2021-05-20

申请号：US17137969

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhong KIM ,  Seyun KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Changsoo LEE

IPC: H05B1/02 ,  H05B3/26

Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.

公开(公告)号：US20190131030A1

公开(公告)日：2019-05-02

申请号：US16162488

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin YUN ,  Seyun KIM ,  Minsu SEOL ,  Changseok LEE ,  Seongheon KIM ,  Hyangsook LEE ,  Changhoon JUNG

IPC: H01B1/24 ,  C08L65/00 ,  C08L25/18 ,  C08K3/04 ,  H01L51/10 ,  H01L51/44 ,  H01L51/52

Abstract: Provided are a conductive composite structure for an electronic device, a method of preparing the conductive composite structure, an electrode for an electronic device including the conductive composite structure, and an electronic device including the conductive composite structure. The conductive composite structure may contain graphene and an organic composite layer including a conductive polymer having a work function of about 5.3 eV or lower, and has a sheet resistance deviation of about 10% or less.

公开(公告)号：US20190037644A1

公开(公告)日：2019-01-31

申请号：US16045834

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhong KIM ,  Seyun KIM ,  Haengdeog KOH ,  Doyoon KIM ,  Hajin KIM ,  Soichiro MIZUSAKI ,  Minjong BAE ,  Changsoo LEE

IPC: H05B1/02

Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.

公开(公告)号：US20250089341A1

公开(公告)日：2025-03-13

申请号：US18818855

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok HEO ,  Minhyun LEE ,  Sangwon KIM ,  Seyun KIM ,  Seokhoon CHOI

IPC: H01L29/49 ,  G11C16/04 ,  H01L21/28 ,  H10B43/27

Abstract: A non-volatile memory device may include a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of insulating layers spaced apart from the channel layer and alternately arranged in the first direction, a charge trap layer between the channel layer and the plurality of gate electrodes, and a charge tunneling layer between the channel layer and the charge trap layer. The plurality of gate electrodes may include M, A, and X, where M may include a metal; A may include a Group 13 element, a Group 14 element, or V, or a combination thereof; X may include carbon or nitrogen, and M, A, and X may be arranged to have a layered crystal structure.

公开(公告)号：US20230337555A1

公开(公告)日：2023-10-19

申请号：US18338707

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Jungho YOON ,  Youngjin CHO

IPC: H01L47/00

CPC classification number: H10N70/231 ,  H10N70/8833 ,  H10B63/80

Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

公开(公告)号：US20230093892A1

公开(公告)日：2023-03-30

申请号：US17685942

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Doyoon KIM ,  Seyun KIM ,  Hyunjae SONG ,  Seungyeul YANG

IPC: H01L27/24 ,  H01L45/00

Abstract: Disclosed are a memory device including a vertical stack structure, a method of manufacturing the same, and/or an electronic device including the memory device. The memory device including a vertical stack structure includes an oxygen scavenger layer on a base substrate, a recording material layer on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer on the recording material layer, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer. The oxygen scavenger layer includes an element that forms oxygen vacancies in the recording material layer and does not include oxygen.