公开(公告)号：US12135542B2

公开(公告)日：2024-11-05

申请号：US17979142

申请日：2022-11-02

Applicant: SanDisk Technologies LLC

Inventor： Tsuyoshi Sendoda ,  Yusuke Ikawa ,  Nagarjuna Asam ,  Kei Samura ,  Masaaki Higashitani

IPC: G05B19/418

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US10074661B2

公开(公告)日：2018-09-11

申请号：US15284067

申请日：2016-10-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Yusuke Ikawa

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524 ,  H01L29/739 ,  H01L29/868

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7391 ,  H01L29/868

Abstract: Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.

公开(公告)号：US09812463B2

公开(公告)日：2017-11-07

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Fei Zhou ,  Somesh Peri ,  Masanori Tsutsumi ,  Keerti Shukla ,  Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US12009269B2

公开(公告)日：2024-06-11

申请号：US17725695

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Masaaki Higashitani ,  Yusuke Ikawa ,  Seyyed Ehsan Esfahani Rashidi ,  Kei Samura ,  Tsuyoshi Sendoda ,  Yanli Zhang

IPC: H01L21/66 ,  H01L27/11578 ,  H10B43/20 ,  H10B43/10

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/26 ,  H10B43/20 ,  H10B43/10

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US20220413036A1

公开(公告)日：2022-12-29

申请号：US17360573

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Yusuke Ikawa ,  Tsuyoshi Sendoda ,  Kei Samura ,  Masaaki Higashitani

IPC: G01R31/27 ,  G01R31/3183 ,  G01R31/317 ,  G01R31/3181 ,  G06N3/063

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US09711530B1

公开(公告)日：2017-07-18

申请号：US15158954

申请日：2016-05-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02598 ,  H01L28/00 ,  H01L29/511 ,  H01L29/518

Abstract: Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device. The compositionally modulated charge storage layer can be formed by providing an oxygen-containing dielectric silicon compound layer outside a tunneling dielectric layer, and subsequently nitriding portions of the oxygen-containing dielectric silicon compound layer only at levels of the control gate electrodes. An alternating stack of sacrificial material layers and insulating layers can be employed to form a memory stack structure therethrough. After removal of the sacrificial material layers, a nitridation process can be performed to convert physically exposed portions of the oxygen-containing dielectric silicon compound layer into silicon nitride portions, which are vertically spaced from one another by remaining oxygen-containing dielectric silicon compound portions that have inferior charge trapping property to the silicon nitride portions.

公开(公告)号：US12105137B2

公开(公告)日：2024-10-01

申请号：US17360573

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Yusuke Ikawa ,  Tsuyoshi Sendoda ,  Kei Samura ,  Masaaki Higashitani

IPC: G01R31/27 ,  G01R31/317 ,  G01R31/3181 ,  G01R31/3183 ,  G06N3/063

CPC classification number: G01R31/275 ,  G01R31/31707 ,  G01R31/31813 ,  G01R31/31835 ,  G06N3/063

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US20230142936A1

公开(公告)日：2023-05-11

申请号：US18152669

申请日：2023-01-10

Applicant: SanDisk Technologies LLC

Inventor： Tsuyoshi Sendoda ,  Yusuke Ikawa ,  Nagarjuna Asam ,  Kei Samura ,  Masaaki Higashitani

IPC: G06T7/00 ,  G06N20/20

CPC classification number: G06T7/0002 ,  G06N20/20

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US20230054342A1

公开(公告)日：2023-02-23

申请号：US17979142

申请日：2022-11-02

Applicant: SanDisk Technologies LLC

Inventor： Tsuyoshi Sendoda ,  Yusuke Ikawa ,  Nagarjuna Asam ,  Kei Samura ,  Masaaki Higashitani

IPC: G05B19/418

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US20220415718A1

公开(公告)日：2022-12-29

申请号：US17725695

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Masaaki Higashitani ,  Yusuke Ikawa ,  Seyyed Ehsan Esfahani Rashidi ,  Kei Samura ,  Tsuyoshi Sendoda ,  Yanli Zhang

IPC: H01L21/66 ,  H01L27/11578

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.