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公开(公告)号：US11837601B2
公开(公告)日：2023-12-05
申请号：US17316079
申请日：2021-05-10
发明人： Jun Akaiwa , Dai Iwata , Hiroshi Nakatsuji , Eiichi Fujikura , Hiroyuki Ogawa
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H01L27/06 , H01L21/8234 , H01L23/522
CPC分类号： H01L27/088 , H01L21/82385 , H01L21/823475 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L23/5226 , H01L27/0629 , H01L27/0928
摘要： A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
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公开(公告)号：US20240111440A1
公开(公告)日：2024-04-04
申请号：US17957424
申请日：2022-09-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0626 , G06F3/0629 , G06F3/0679
摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
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公开(公告)号：US20220359501A1
公开(公告)日：2022-11-10
申请号：US17316079
申请日：2021-05-10
发明人： Jun Akaiwa , Dai Iwata , Hiroshi Nakatsuji , Eiichi Fujikura , Hiroyuki Ogawa
IPC分类号： H01L27/088 , H01L27/092 , H01L27/06 , H01L21/8234 , H01L21/8238 , H01L23/522
摘要： A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
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公开(公告)号：US12094944B2
公开(公告)日：2024-09-17
申请号：US17316015
申请日：2021-05-10
发明人： Dai Iwata , Hiroshi Nakatsuji , Hiroyuki Ogawa , Eiichi Fujikura
IPC分类号： H01L27/092 , H01L21/8238 , H01L27/06 , H01L27/07 , H01L29/40 , H01L29/423 , H01L29/66
CPC分类号： H01L29/42356 , H01L21/82385 , H01L21/823857 , H01L21/823871 , H01L21/823878 , H01L27/0629 , H01L27/0727 , H01L27/0922 , H01L29/401 , H01L29/42376 , H01L29/66553 , H01L29/6656
摘要： A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
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公开(公告)号：US12032837B2
公开(公告)日：2024-07-09
申请号：US17957424
申请日：2022-09-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0626 , G06F3/0629 , G06F3/0679
摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
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公开(公告)号：US10256167B1
公开(公告)日：2019-04-09
申请号：US15933947
申请日：2018-03-23
发明人： Noritaka Fukuo , Hokuto Kodate , Eiichi Fujikura , Akinori Yutani , Kengo Miura , Masaomi Koizumi , Hidehito Koseki
IPC分类号： H01L23/31 , H01L21/765 , H01L21/761 , H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11526 , H01L29/06 , H01L23/00 , H01L27/092 , H01L23/535 , H01L29/51 , H01L29/40 , H01L21/8238 , H01L21/56 , H01L21/02 , H01L21/3105 , H01L21/768
摘要： A semiconductor structure includes a field effect transistor located on a semiconductor substrate, a silicon oxide liner contacting at least a portion of the semiconductor substrate, a silicon nitride liner contacting a top surface and a sidewall of the silicon oxide liner and contacting a top surface of the semiconductor substrate in a seal region, a silicon nitride diffusion barrier layer including a planar bottom surface that contacts top surfaces of vertically extending portions of the silicon nitride liner, and a silicon oxide material portion overlying the silicon nitride diffusion barrier layer. A combination of the silicon nitride liner and the silicon nitride diffusion barrier layer constitutes a hydrogen diffusion barrier structure that continuously extends from the seal region and over the field effect transistor.
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