-
公开(公告)号：US12032837B2
公开(公告)日：2024-07-09
申请号：US17957424
申请日：2022-09-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0626 , G06F3/0629 , G06F3/0679
摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
-
公开(公告)号：US11069707B2
公开(公告)日：2021-07-20
申请号：US16666522
申请日：2019-10-29
IPC分类号： H01L27/11582 , H01L27/11556 , H01L23/528 , H01L23/522 , H01L29/788 , H01L23/00 , H01L25/18 , H01L21/02 , H01L25/00 , H01L21/768 , H01L27/11519 , H01L27/11565 , H01L21/311 , H01L21/82
摘要： A semiconductor die includes alternating stacks of insulating layers and electrically conductive layers that are laterally separated from each other by first backside trenches that laterally extend along a first horizontal direction, an array of memory stack structures vertically extending through the alternating sacks, an inner edge seal structure that continuously laterally surrounds the alternating stacks, an outer edge seal structure that continuously laterally surrounds the inner edge seal structure, and additional alternating stacks of insulating layers and electrically conductive layers located between the inner edge seal structure and the outer edge seal structure.
-
公开(公告)号：US10515897B2
公开(公告)日：2019-12-24
申请号：US15982215
申请日：2018-05-17
发明人： Masatoshi Nishikawa , Akio Nishida , Murshed Chowdhury , Takahito Fujita , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L29/792 , H01L23/532 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L21/768 , H01L23/522 , H01L29/06 , H01L29/08
摘要： A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.
-
公开(公告)号：US20240111440A1
公开(公告)日：2024-04-04
申请号：US17957424
申请日：2022-09-30
IPC分类号： G06F3/06
CPC分类号： G06F3/0626 , G06F3/0629 , G06F3/0679
摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.
-
公开(公告)号：US10515907B2
公开(公告)日：2019-12-24
申请号：US15982188
申请日：2018-05-17
IPC分类号： H01L23/00 , H01L23/522 , H01L27/11556 , H01L21/768 , H01L27/1157 , H01L27/11524 , H01L27/11582
摘要： A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.
-
6.发明申请公开(公告)号：US20190319040A1
公开(公告)日：2019-10-17
申请号：US15950356
申请日：2018-04-11
发明人： Yasushi Ishii , Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L27/11582 , H01L29/10 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/768 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.
-
公开(公告)号：US10256099B1
公开(公告)日：2019-04-09
申请号：US15916720
申请日：2018-03-09
发明人： Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/265 , H01L27/088 , H01L29/49 , H01L29/78 , H01L21/3213 , H01L21/308 , H01L29/66
摘要： A semiconductor structure, such as a CMOS device, includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first composite gate electrode containing a first vertical stack of a p-doped semiconductor gate electrode, a first interfacial dielectric layer, and a first metallic gate electrode. The second field effect transistor includes a second composite gate electrode containing a second vertical stack that includes an n-doped semiconductor gate electrode and a second metallic gate electrode. A second interfacial dielectric layer having a second thickness that is thinner than the first interfacial dielectric layer may, or may not, be present in the second composite gate electrode.
-
公开(公告)号：US11876096B2
公开(公告)日：2024-01-16
申请号：US17496122
申请日：2021-10-07
IPC分类号： H01L27/092 , H01L29/49 , H01L29/78 , H01L21/265 , H01L29/66 , H01L21/8238 , H01L21/266
CPC分类号： H01L27/092 , H01L21/266 , H01L21/26513 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/4983 , H01L29/66492 , H01L29/7833
摘要： A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.
-
公开(公告)号：US11710740B2
公开(公告)日：2023-07-25
申请号：US17496099
申请日：2021-10-07
IPC分类号： H01L27/092 , H01L29/49 , H01L29/78 , H01L21/265 , H01L29/66 , H01L21/8238 , H01L21/266
CPC分类号： H01L27/092 , H01L21/266 , H01L21/26513 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/4983 , H01L29/66492 , H01L29/7833
摘要： A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.
-
10.发明授权公开(公告)号：US10804284B2
公开(公告)日：2020-10-13
申请号：US15950356
申请日：2018-04-11
发明人： Yasushi Ishii , Jun Akaiwa , Kiyokazu Shishido , Hiroyuki Ogawa
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/528 , H01L21/311 , H01L21/768 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/10 , H01L21/3105 , H01L21/02
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and a contact well set that includes contact wells extending through a respective upper region of the alternating stack. Each of the contact wells contains first stepped surfaces which have a stepwise descending vertical profile along a first horizontal direction and second stepped surfaces which have a stepwise descending vertical profile along a second horizontal direction which is perpendicular to the first horizontal direction.
-
-
-
-
-
-
-
-
-
搜索结果
13 条记录 (耗时 0.018 秒)
