公开(公告)号：US11088152B2

公开(公告)日：2021-08-10

申请号：US16887558

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi Nakatsuji ,  Yasuyuki Aoki ,  Shigeki Shimomura ,  Akira Inoue ,  Kazutaka Yoshizawa ,  Hiroyuki Ogawa

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L21/768 ,  H01L27/11 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US09991280B2

公开(公告)日：2018-06-05

申请号：US15434544

申请日：2017-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi Nakamura ,  Jin Liu ,  Kazuya Tokunaga ,  Marika Gunji-Yoneoka ,  Matthias Baenninger ,  Hiroyuki Kinoshita ,  Murshed Chowdhury ,  Jiyin Xu ,  Dai Iwata ,  Hiroyuki Ogawa ,  Kazutaka Yoshizawa ,  Yasuaki Yonemochi

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L49/02

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US10714486B2

公开(公告)日：2020-07-14

申请号：US16130104

申请日：2018-09-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi Nakatsuji ,  Yasuyuki Aoki ,  Shigeki Shimomura ,  Akira Inoue ,  Kazutaka Yoshizawa ,  Hiroyuki Ogawa

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L21/768 ,  H01L27/11 ,  H01L21/8234

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

公开(公告)号：US12032837B2

公开(公告)日：2024-07-09

申请号：US17957424

申请日：2022-09-30

Applicant: SanDisk Technologies LLC

Inventor： Yuki Mizutani ,  Kazutaka Yoshizawa ,  Kiyokazu Shishido ,  Eiichi Fujikura

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0629 ,  G06F3/0679

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

公开(公告)号：US10748919B2

公开(公告)日：2020-08-18

申请号：US15989905

申请日：2018-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dai Iwata ,  Hiroyuki Ogawa ,  Kazutaka Yoshizawa ,  Yasuaki Yonemochi

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764 ,  H01L23/29 ,  H01L23/31 ,  H01L49/02

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US20180277566A1

公开(公告)日：2018-09-27

申请号：US15989905

申请日：2018-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dai Iwata ,  Hiroyuki Ogawa ,  Kazutaka Yoshizawa ,  Yasuaki Yonemochi

IPC: H01L27/11582 ,  H01L49/02 ,  H01L23/31 ,  H01L23/29 ,  H01L21/764 ,  H01L29/423 ,  H01L23/528 ,  H01L29/10 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/764 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/528 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/42372

Abstract: An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

公开(公告)号：US20240111440A1

公开(公告)日：2024-04-04

申请号：US17957424

申请日：2022-09-30

Applicant: SanDisk Technologies LLC

Inventor： Yuki Mizutani ,  Kazutaka Yoshizawa ,  Kiyokazu Shishido ,  Eiichi Fujikura

IPC: G06F3/06

CPC classification number: G06F3/0626 ,  G06F3/0629 ,  G06F3/0679

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

公开(公告)号：US10355100B1

公开(公告)日：2019-07-16

申请号：US15982266

申请日：2018-05-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu Ueda ,  Tomoyuki Obu ,  Kazutaka Yoshizawa ,  Yasuyuki Aoki ,  Eisuke Takii ,  Akio Nishida

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/115 ,  H01L27/092 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529

Abstract: A first field effect transistor and a second field effect transistor are formed on a substrate. A silicon nitride liner is formed over the first field effect transistor and the second field effect transistor. An upper portion of the silicon nitride liner is converted into a thermal silicon oxide liner. A lower portion of the silicon nitride liner remains as a silicon nitride material portion. A first portion of the thermal silicon oxide liner is removed from above the second field effect transistor, and a second portion of the thermal silicon oxide liner remains above the first field effect transistor. Selective presence of the silicon oxide liner provides differential stress within the channels of the first and second field effect transistors, which can be employed to optimize performance of different types of field effect transistors.

公开(公告)号：US10290645B2

公开(公告)日：2019-05-14

申请号：US15638672

申请日：2017-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroshi Nakatsuji ,  Kazutaka Yoshizawa ,  Hiroyuki Ogawa

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.