公开(公告)号：US11776640B2

公开(公告)日：2023-10-03

申请号：US17511749

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Kei Kitamura ,  Yuki Fujita ,  Kyosuke Matsumoto ,  Masahiro Kano ,  Minoru Yamashita ,  Ryuji Yamashita ,  Shuzo Otsuka

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G06F3/06 ,  G11C16/08

CPC classification number: G11C16/3431 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/08

Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

公开(公告)号：US20230110995A1

公开(公告)日：2023-04-13

申请号：US17486090

申请日：2021-09-27

Applicant: SanDisk Technologies LLC

Inventor： Yuki Fujita ,  Kei Kitamura ,  Kyosuke Matsumoto ,  Masahiro Kano ,  Minoru Yamashita ,  Ryuji Yamashita ,  Shuzo Otsuka

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

Abstract: A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

公开(公告)号：US20230368852A1

公开(公告)日：2023-11-16

申请号：US17745120

申请日：2022-05-16

Applicant: SanDisk Technologies LLC

Inventor： Kei Kitamura ,  Iris Lu ,  Tai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C7/10

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/24 ,  G11C7/1048 ,  G11C7/1039

Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

公开(公告)号：US20230131117A1

公开(公告)日：2023-04-27

申请号：US17511749

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Kei Kitamura ,  Yuki Fujita ,  Kyosuke Matsumoto ,  Masahiro Kano ,  Minoru Yamashita ,  Ryuji Yamashita ,  Shuzo Otsuka

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06

Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

公开(公告)号：US12014795B2

公开(公告)日：2024-06-18

申请号：US17486090

申请日：2021-09-27

Applicant: SanDisk Technologies LLC

Inventor： Yuki Fujita ,  Kei Kitamura ,  Kyosuke Matsumoto ,  Masahiro Kano ,  Minoru Yamashita ,  Ryuji Yamashita ,  Shuzo Otsuka

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C7/06 ,  G11C7/1048 ,  G11C7/12 ,  G11C16/102 ,  G11C16/26

Abstract: A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

公开(公告)号：US11915769B2

公开(公告)日：2024-02-27

申请号：US17745120

申请日：2022-05-16

Applicant: SanDisk Technologies LLC

Inventor： Kei Kitamura ,  Iris Lu ,  Tai-Yuan Tseng

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C7/1048 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.