公开(公告)号：US20220139878A1

公开(公告)日：2022-05-05

申请号：US17090045

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki OGAWA ,  Ken OOWADA ,  Mitsuteru MUSHIGA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

公开(公告)号：US20200185405A1

公开(公告)日：2020-06-11

申请号：US16215912

申请日：2018-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Masatoshi NISHIKAWA ,  Ken OOWADA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.

公开(公告)号：US20220139441A1

公开(公告)日：2022-05-05

申请号：US17090080

申请日：2020-11-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki OGAWA ,  Ken OOWADA ,  Mitsuteru MUSHIGA

IPC: G11C11/408 ,  G11C11/4094 ,  G11C5/02 ,  G11C5/06

Abstract: A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.

公开(公告)号：US20200168623A1

公开(公告)日：2020-05-28

申请号：US16202713

申请日：2018-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi NISHIKAWA ,  Michiaki SANO ,  Ken OOWADA ,  Zhixin CUI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/8234

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

公开(公告)号：US20200005871A1

公开(公告)日：2020-01-02

申请号：US16024002

申请日：2018-06-29

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG ,  Aaron LEE ,  Gerrit Jan HEMINK ,  Ken OOWADA ,  Toru MIWA

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.