公开(公告)号：US06629047B1

公开(公告)日：2003-09-30

申请号：US09539475

申请日：2000-03-30

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

IPC: G11C1300

CPC classification number: G11C5/147 ,  G11C16/225

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract translation: 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。

公开(公告)号：US06789027B2

公开(公告)日：2004-09-07

申请号：US10436745

申请日：2003-05-12

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

IPC: G11C1300

CPC classification number: G11C5/147 ,  G11C16/225

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract translation: 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。

公开(公告)号：US06459645B2

公开(公告)日：2002-10-01

申请号：US09410493

申请日：1999-09-30

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC: G11C800

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C8/12

Abstract: A method and apparatus to segment a programmable non-volatile memory array into at least two banks. The banks include memory cells. Each bank in the at least two banks is provided with a local programming voltage. Each local programming voltage is independent of the other local programming voltages supplied to the other banks.

Abstract translation: 一种将可编程非易失性存储器阵列分割成至少两个存储体的方法和装置。 银行包括存储单元。 至少两个组中的每个存储体都具有本地编程电压。 每个本地编程电压与提供给其他存储体的其他本地编程电压无关。

公开(公告)号：US6163225A

公开(公告)日：2000-12-19

申请号：US305976

申请日：1999-05-05

Applicant: Rajesh Sundaram ,  Sandeep K. Guliani

Inventor： Rajesh Sundaram ,  Sandeep K. Guliani

IPC: H03B5/04 ,  H03B5/24

CPC classification number: H03B5/04 ,  H03B5/24

Abstract: A method for generating a positive temperature correlated clock frequency is described. The method comprises conducting current through a resistor to charge a capacitor. When the capacitor is charged to a trip point of the inverter at the input of the inverter chain, a transition in an output signal of an inverter chain is triggered. The capacitor is discharged through a grounding device when the output signal activates said grounding device.

Abstract translation: 描述了用于产生正温度相关时钟频率的方法。 该方法包括通过电阻器传导电流以对电容器充电。 当电抗器在变频器链的输入端被充电到变频器的跳变点时，触发逆变器链输出信号的转变。 当输出信号激活所述接地装置时，电容器通过接地装置放电。

公开(公告)号：US06463004B2

公开(公告)日：2002-10-08

申请号：US09924922

申请日：2001-08-07

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC: G11C800

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C8/12

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US06434073B1

公开(公告)日：2002-08-13

申请号：US09924888

申请日：2001-08-07

Applicant: Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

Inventor： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC: G11C702

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US09274885B2

公开(公告)日：2016-03-01

申请号：US13997246

申请日：2011-12-30

Applicant: Shekoufeh Qawami ,  Rajesh Sundaram

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G11C13/00

CPC classification number: G06F11/1048 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1068 ,  G11C13/0004

Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。

公开(公告)号：US20130238832A1

公开(公告)日：2013-09-12

申请号：US13413898

申请日：2012-03-07

Applicant: Ravikanth Dronamraju ,  Douglas P. Doucette ,  Rajesh Sundaram

Inventor： Ravikanth Dronamraju ,  Douglas P. Doucette ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F3/0685 ,  G06F12/0866 ,  G06F2212/217 ,  G06F2212/461

Abstract: Methods and apparatuses for performing deduplication in a hybrid storage aggregate are provided. In one example, a method includes operating a hybrid storage aggregate that includes a plurality of tiers of different types of physical storage media. The method includes identifying a first storage block and a second storage block of the hybrid storage aggregate that contain identical data and identifying caching statuses of the first storage block and the second storage block. The method also includes deduplicating the first storage block and the second storage block based on the caching statuses of the first storage block and the second storage block.

Abstract translation: 提供了用于在混合存储集合中执行重复数据消除的方法和装置。 在一个示例中，方法包括操作包括多个不同类型的物理存储介质的混合存储集合。 该方法包括识别包含相同数据并识别第一存储块和第二存储块的高速缓存状态的混合存储聚合的第一存储块和第二存储块。 该方法还包括基于第一存储块和第二存储块的高速缓存状态对第一存储块和第二存储块进行重复数据删除。

公开(公告)号：US07979633B2

公开(公告)日：2011-07-12

申请号：US10817212

申请日：2004-04-02

Applicant: Steven R. Kleiman ,  Rajesh Sundaram ,  Douglas P. Doucette ,  Stephen H. Strange ,  Srinivasan Viswanathan

Inventor： Steven R. Kleiman ,  Rajesh Sundaram ,  Douglas P. Doucette ,  Stephen H. Strange ,  Srinivasan Viswanathan

IPC: G06F12/16

CPC classification number: G06F3/0613 ,  G06F3/0643 ,  G06F3/0655 ,  G06F3/0689 ,  G06F11/1076

Abstract: The invention features a method for controlling storage of data in a plurality of storage devices each including storage blocks, for example, in a RAID array. The method includes receiving a plurality of write requests associated with data, and buffering the write requests. A file system defines a group of storage blocks, responsive to disk topology information. The group includes a plurality of storage blocks in each of the plurality of storage devices. Each data block of the data to be written is associated with a respective one of the storage blocks, for transmitting the association to the plurality of storage devices.

Abstract translation: 本发明的特征在于一种用于控制多个存储设备中的数据存储的方法，每个存储设备包括例如RAID阵列中的存储块。 该方法包括接收与数据相关联的多个写入请求，并缓冲写入请求。 文件系统根据磁盘拓扑信息定义一组存储块。 该组包括多个存储装置中的每一个中的多个存储块。 要写入的数据的每个数据块与相应的一个存储块相关联，用于将关联发送到多个存储设备。

公开(公告)号：US07945822B1

公开(公告)日：2011-05-17

申请号：US12430783

申请日：2009-04-27

Applicant: Jeffrey S. Kimmel ,  Rajesh Sundaram ,  George Totolos, Jr. ,  Michael W. J. Hordijk

Inventor： Jeffrey S. Kimmel ,  Rajesh Sundaram ,  George Totolos, Jr. ,  Michael W. J. Hordijk

IPC: G11C29/00

CPC classification number: G06F12/0246 ,  G06F11/1666 ,  G06F11/20 ,  G06F2212/1032 ,  G06F2212/7208 ,  G11C29/76

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract translation: 这里描述了使用非对齐数据条带化将数据存储到低延迟随机读取存储器（LLRRM）装置的方法和装置，LLRRM装置在存储系统上实现。 LLRRM设备可以包括一个包括多个存储器芯片的存储体，每个芯片可以同时访问以存储多个擦除单元（EU）上的数据。 存储操作系统可以为每个芯片保留列出保留EU的备用数据结构和用于跟踪缺陷EU之间的重新映射的重映射数据结构，以在芯片中保留EU。 芯片中的有缺陷的EU可以从保留数据结构映射到保留EU。 在接收到在缺陷EU处存储到LLRRM设备的数据块时，存储操作系统可以使用重新映射的保留EU以不对齐的方式跨越多个芯片对接收到的数据块进行条带化。