公开(公告)号：US06629047B1

公开(公告)日：2003-09-30

申请号：US09539475

申请日：2000-03-30

申请人： Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

发明人： Sandeep K. Guliani ,  Rajesh Sundaram ,  Hari M. Rao ,  Johnny Javanifard

IPC分类号： G11C1300

CPC分类号： G11C5/147 ,  G11C16/225

摘要： A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

摘要翻译： 一种电压检测和锁定的方法。 一个实施例的方法首先将参考电压与电源电压进行比较，以确定电压电源电压是否大于参考电压。 参考电压通过确定参考电压是否至少是有效的电压电位来验证。 如果电源电压大于参考电压，并且参考电压有效，则产生解锁信号。

公开(公告)号：US6150835A

公开(公告)日：2000-11-21

申请号：US75430

申请日：1998-05-08

申请人： Peter K. Hazen ,  Sandeep K. Guliani ,  Robert E. Larsen

发明人： Peter K. Hazen ,  Sandeep K. Guliani ,  Robert E. Larsen

IPC分类号： G11C7/00 ,  G05F1/10 ,  G05F3/02 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00 ,  H03K5/22

CPC分类号： H03K19/17748 ,  H03K19/1778

摘要： A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

摘要翻译： 描述了包括电压输入和耦合到电压输入的检测电路的可编程逻辑器件。 检测电路检测施加到电压输入的电压是否超过预定值。 可编程逻辑器件还包括耦合到检测电路的配置电路。 配置电路配置可编程逻辑器件，以响应于检测电路检测到电压超过预定值，通过电压输入接收足以进行编程和擦除操作的电流。

公开(公告)号：US5109187A

公开(公告)日：1992-04-28

申请号：US589698

申请日：1990-09-28

申请人： Sandeep K. Guliani

发明人： Sandeep K. Guliani

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C16/30

CPC分类号： G11C5/147 ,  G05F3/247 ,  G11C16/30

摘要： A circuit is described as a generating supply-independent voltage reference. In MOS technology, a current mirror section incorporating a pair of N-channel and W-channel tracking devices are coupled to a power supply V.sub.cc for generating a voltage reference output that is directly proportional to V.sub.tn -V.sub.tw. V.sub.tn is the gate threshold voltage of the N-channel device, while V.sub.tw is the gate threshold voltage of W-channel device. A start-up circuit is further coupled to the power supply V.sub.cc and to the current mirror section for maintaining the operating point V.sub.1 of the circuit that is independent of supply voltage. The degree of supply independence can be further increased by adding a pair of P-channel device to the output of the present invention. Thus, the present invention generates a voltage reference that is independent from power supply, temperature and process while minimizing power dissipation. When the present invention replaces the power supply to the sensing circuit of non-volatile memory devices such as an EPROM the overshoot encountered during the read mode is minimized. It follows that the present invention not only solves one of the key yield losses seen on non-volatile memory devices but also improves the access time for the same devices.

摘要翻译： 电路被描述为产生电源独立电压基准。 在MOS技术中，结合有一对N沟道和W沟道跟踪器件的电流镜部分耦合到电源Vcc，用于产生与Vtn-Vtw成正比的电压基准输出。 Vtn是N沟道器件的栅极阈值电压，而Vtw是W沟道器件的栅极阈值电压。 启动电路还耦合到电源Vcc和电流镜部分，用于维持电路的工作点V1，其独立于电源电压。 通过向本发明的输出添加一对P沟道器件，可以进一步提高供给的独立性。 因此，本发明在功率耗散最小化的同时产生独立于电源，温度和过程的电压基准。 当本发明替代诸如EPROM的非易失性存储器件的感测电路的电源时，读取模式期间遇到的过冲被最小化。 因此，本发明不仅解决了在非易失性存储器件上看到的关键产量损失之一，而且改善了相同器件的访问时间。

公开(公告)号：US06463004B2

公开(公告)日：2002-10-08

申请号：US09924922

申请日：2001-08-07

申请人： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

发明人： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC分类号： G11C800

CPC分类号： G11C16/30 ,  G11C5/14 ,  G11C8/12

摘要： A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US06434073B1

公开(公告)日：2002-08-13

申请号：US09924888

申请日：2001-08-07

申请人： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

发明人： Sandeep K. Guliani ,  Rajesh Sundaram ,  Mase J. Taub

IPC分类号： G11C702

摘要： A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank including memory cells. The banks are provided with a supply voltage.

公开(公告)号：US5373508A

公开(公告)日：1994-12-13

申请号：US923853

申请日：1992-07-31

申请人： Sandeep K. Guliani

发明人： Sandeep K. Guliani

IPC分类号： H04L25/06 ,  H01S3/10

CPC分类号： H04L25/062

摘要： Two parallel valid data detectors are provided to detect whether a sinusoidal electrical signal from a twisted pair medium represents valid data. One handles phase 0 degree starting sinusoidal electrical signal, the other handle phase 180 degree. In either case, the valid data detectors receive two series of pulses as input, indicating positive and negative differences respectively between RD and RD from the twisted pair medium. In response, if the valid data detector detects the proper data pattern within a predetermined time frame, it outputs a signal indicating the detection of valid data. The "phase 0" valid data detector looks for a high to low and back to high data pattern, whereas, the "phase 180" valid data detector looks for a low to high and back to low data pattern. Additionally, a signal magnitude detector is provided to detect magnitude differences between RD+ and RD- from the twisted pair medium, and generate the positive and a negative series of pulses for the valid data detectors, as long as the magnitude differences exceeded a predetermined minimum threshold. Furthermore, a signal synchronizer is provided to receive the valid data detection signal from either valid data detector, and synchronize the generated signal to the internal clock of the receiving circuit.

摘要翻译： 提供两个并行的有效数据检测器来检测来自双绞线介质的正弦电信号是否表示有效数据。 一个处理相位0度起始正弦电信号，另一个手柄相位180度。 在任一种情况下，有效的数据检测器都接收两个串联的脉冲作为输入，分别表示来自双绞线介质的RD和RD之间的正负差异。 作为响应，如果有效数据检测器在预定时间帧内检测到适当的数据模式，则输出指示检测有效数据的信号。 “0”有效数据检测器寻找高到低的数据模式，而“相180”有效的数据检测器寻找低到高和回到低的数据模式。 此外，提供信号幅度检测器以检测来自双绞线介质的RD +和RD-之间的幅度差异，并产生用于有效数据检测器的正序列和负序脉冲，只要幅度差超过预定的最小阈值 。 此外，提供信号同步器以从有效数据检测器接收有效数据检测信号，并将所生成的信号同步到接收电路的内部时钟。

公开(公告)号：US06255896B1

公开(公告)日：2001-07-03

申请号：US09406329

申请日：1999-09-27

申请人： Bo Li ,  Marc E. Landgraf ,  Mase Taub ,  Sandeep K. Guliani

发明人： Bo Li ,  Marc E. Landgraf ,  Mase Taub ,  Sandeep K. Guliani

IPC分类号： G05F302

CPC分类号： H02M3/073

摘要： The present invention provides a method, apparatus, and system for rapid transition of a charge pump circuit from a low power state to a high power state. The charge pump circuit has at least one pump stage. The at least one pump stage includes at least a first capacitor coupled to a gate of a first switching transistor forming a boot node and at least a second capacitor coupled to an output node of the at least one pump stage. It is determined whether the charge pump circuit is in the low power state or the high power state. If the charge pump circuit is in the low power state, a first predetermined voltage and a second predetermined voltage that are different than the ground voltage level are applied to the boot node and the output node, respectively. If the charge pump circuit is in the high power state, the first predetermined voltage and the second predetermined voltage are removed from the boot node and the output node, respectively.

摘要翻译： 本发明提供了一种用于将电荷泵电路从低功率状态快速转变到高功率状态的方法，装置和系统。 电荷泵电路具有至少一个泵级。 所述至少一个泵级包括耦合到形成引导节点的第一开关晶体管的栅极的至少第一电容器和耦合到所述至少一个泵级的输出节点的至少第二电容器。 确定电荷泵电路是处于低功率状态还是处于高功率状态。 如果电荷泵电路处于低功率状态，则分别将不同于接地电压电平的第一预定电压和第二预定电压施加到引导节点和输出节点。 如果电荷泵电路处于高功率状态，则分别从引导节点和输出节点去除第一预定电压和第二预定电压。

公开(公告)号：US06223290B1

公开(公告)日：2001-04-24

申请号：US09074475

申请日：1998-05-07

申请人： Robert E. Larsen ,  Peter K. Hazen ,  Sandeep K. Guliani ,  Robert N. Hasbun ,  Sanjay S. Talreja ,  Collin Ong ,  Charles W. Brown ,  Terry L. Kendall

发明人： Robert E. Larsen ,  Peter K. Hazen ,  Sandeep K. Guliani ,  Robert N. Hasbun ,  Sanjay S. Talreja ,  Collin Ong ,  Charles W. Brown ,  Terry L. Kendall

IPC分类号： H04B116

CPC分类号： H04W12/12 ,  H04W88/02

摘要： A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

摘要翻译： 描述了一种用于控制电子系统的使用的方法和装置。 通过将至少一个唯一代码编程到电子系统的辅助存储器中来控制电子系统的使用。 辅助存储器是位于主存储器阵列空间外部的永久可锁存储器。 将唯一代码与至少一个组件代码进行比较。 基于唯一代码和组件代码之间的预定关系来控制电子系统的使用。

公开(公告)号：US6072723A

公开(公告)日：2000-06-06

申请号：US306322

申请日：1999-05-06

申请人： Sandeep K. Guliani ,  Binh N. Ngo

发明人： Sandeep K. Guliani ,  Binh N. Ngo

IPC分类号： G11C16/00

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/26

摘要： A bias circuit for a memory cell having first and second floating gate devices, and third and fourth reference devices, one of which has an output terminal coupled thereto is described. In one embodiment, the bias circuit includes a first capacitor including a first terminal coupled to the gates of the first and second devices, and a second terminal coupled to a power supply terminal, and a second capacitor including a first terminal coupled to the gates of the third and fourth devices, and a second terminal coupled to the power supply terminal. The bias circuit further includes a reference circuit including a first terminal having a first signal thereon and coupled to the gates of the first and second devices, and a second terminal having a second signal thereon and coupled to the gates of the third and fourth devices, the reference circuit to periodically turn on the first and second signals. The bias circuit reduces standby current and wake up time of redundant circuits in non-volatile memory devices.

摘要翻译： 一种用于具有第一和第二浮动栅极器件的存储器单元的偏置电路，以及第三和第四参考器件，其中一个具有与其耦合的输出端子。 在一个实施例中，偏置电路包括第一电容器，其包括耦合到第一和第二器件的栅极的第一端子和耦合到电源端子的第二端子，以及包括耦合到栅极的第一端子的第二电容器 第三和第四器件，以及耦合到电源端子的第二端子。 偏置电路还包括参考电路，其包括在其上具有第一信号并且耦合到第一和第二器件的栅极的第一端子，以及在其上具有第二信号并且耦合到第三和第四器件的栅极的第二端子， 该参考电路周期性地接通第一和第二信号。 偏置电路可以降低非易失性存储器件中冗余电路的待机电流和唤醒时间。

公开(公告)号：US20150348627A1

公开(公告)日：2015-12-03

申请号：US14289858

申请日：2014-05-29

申请人： Mase J Taub ,  Sandeep K. Guliani ,  Kiran Pangal

发明人： Mase J Taub ,  Sandeep K. Guliani ,  Kiran Pangal

IPC分类号： G11C13/00

CPC分类号： G11C13/0004 ,  G11C5/02 ,  G11C7/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77

摘要： A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

摘要翻译： 公开了用于在交叉点存储器中写入数据的系统和技术。 检测交叉点存储器的一个或多个存储单元的状态，然后继续选择并保持。 然后，基于要写入一个或多个存储器单元的输入用户数据，确定一个或多个存储器单元中的哪一个将改变状态。 然后通过向存储器单元施加写入电流脉冲来写入确定为改变状态并且仍被选择为导通的一个或多个存储器单元。 在一个示例性实施例中，一个或多个存储器单元包括一个或多个相变型存储单元器件。