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19 条记录 (耗时 0.023 秒)

    Method and apparatus for fast production programming and low-voltage in-system writes for programmable logic device
    2.
    发明授权
    Method and apparatus for fast production programming and low-voltage in-system writes for programmable logic device 失效
    用于可编程逻辑器件的快速生产编程和低压系统写入的方法和装置

    公开(公告)号：US6150835A

    公开(公告)日：2000-11-21

    申请号：US75430

    申请日：1998-05-08

    申请人： Peter K. Hazen ,  Sandeep K. Guliani ,  Robert E. Larsen

    发明人： Peter K. Hazen ,  Sandeep K. Guliani ,  Robert E. Larsen

    IPC分类号： G11C7/00 ,  G05F1/10 ,  G05F3/02 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00 ,  H03K5/22

    CPC分类号： H03K19/17748 ,  H03K19/1778

    摘要： A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

    摘要翻译： 描述了包括电压输入和耦合到电压输入的检测电路的可编程逻辑器件。 检测电路检测施加到电压输入的电压是否超过预定值。 可编程逻辑器件还包括耦合到检测电路的配置电路。 配置电路配置可编程逻辑器件，以响应于检测电路检测到电压超过预定值，通过电压输入接收足以进行编程和擦除操作的电流。

    Floating gate nonvolatile memory with configurable erasure blocks
    5.
    发明授权
    Floating gate nonvolatile memory with configurable erasure blocks 失效
    浮动非易失性存储器，具有可配置的擦除块

    公开(公告)号：US5280447A

    公开(公告)日：1994-01-18

    申请号：US901275

    申请日：1992-06-19

    申请人： Peter K. Hazen ,  Sanjay S. Talreja ,  Sherif R. B. Sweha

    发明人： Peter K. Hazen ,  Sanjay S. Talreja ,  Sherif R. B. Sweha

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/12 ,  G11C11/34

    CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C5/063

    摘要： A nonvolatile memory includes a first block and a second block. The first block comprises a first memory cell and a first source line coupled to a source of the first memory cell. The second block comprises a second memory cell and a second source line coupled to a source of the second memory cell. A first source switch is coupled to the first source line for selectively coupling a first potential, a second potential, and a third potential to the first source line. The second potential has a voltage intermediate between the first potential and the third potential. A second source switch is coupled to the second source line for selectively coupling one of the first, second, and third potentials to the second source line. A block select circuit receives a block address for selecting one of the first and second source switches to couple one of the first, second, and third potentials to its respective one of the first and second source lines. A configuration cell is coupled to the block select circuit for configuring block operations of the first and second blocks. When the configuration cell is in a first voltage state, the configuration cell causes the block select circuit to separately select one of the first and second source switches depending upon the address received. When the configuration cell is in a second voltage state, the configuration cell causes the block select circuit to collectively select the first and second source switches.

    摘要翻译： 非易失性存储器包括第一块和第二块。 第一块包括耦合到第一存储器单元的源的第一存储单元和第一源极线。 第二块包括耦合到第二存储单元的源的第二存储单元和第二源极线。 第一源开关耦合到第一源极线，用于选择性地将第一电位，第二电位和第三电位耦合到第一源极线。 第二电位具有介于第一电势和第三电位之间的电压。 第二源开关耦合到第二源极线，用于选择性地将第一，第二和第三电位中的一个耦合到第二源极线。 块选择电路接收用于选择第一和第二源开关之一的块地址，以将第一，第二和第三电位中的一个耦合到其第一和第二源极线中的相应一个。 配置单元耦合到块选择电路，用于配置第一和第二块的块操作。 当配置单元处于第一电压状态时，配置单元使得块选择电路根据所接收的地址分别选择第一和第二源开关之一。 当配置单元处于第二电压状态时，配置单元使块选择电路集体选择第一和第二源开关。

    Method and apparatus for preempting operations in a nonvolatile memory in order to read code from the nonvolatile memory
    7.
    发明授权
    Method and apparatus for preempting operations in a nonvolatile memory in order to read code from the nonvolatile memory 失效
    用于在非易失性存储器中抢占操作以从非易失性存储器读取代码的方法和装置

    公开(公告)号：US5940861A

    公开(公告)日：1999-08-17

    申请号：US717268

    申请日：1996-09-20

    申请人： Charles W. Brown ,  Peter K. Hazen

    发明人： Charles W. Brown ,  Peter K. Hazen

    IPC分类号： G11C16/10 ,  G11C16/26 ,  G06F12/02

    CPC分类号： G11C16/26 ,  G11C16/10 ,  G11C2216/20

    摘要： A method and apparatus suspend operations in a flash memory in order to read code from the flash memory. A system comprises a processor and a nonvolatile writeable memory coupled together. A non-read operation is preempted in the nonvolatile writeable memory responsive to an input at a pin of the nonvolatile writeable memory. The preemption occurs by either suspending the non-read operation or aborting the non-read operation. Code is read from the nonvolatile writeable memory and provided to the processor. Subsequently, the non-read operation is resumed at where it was suspended, or is started anew.

    摘要翻译： 一种方法和装置将闪存中的操作暂停以便从闪速存储器读取代码。 系统包括耦合在一起的处理器和非易失性可写存储器。 响应于在非易失性可写存储器的引脚处的输入，非易失性可写存储器中的非读操作被抢占。 抢占是通过暂停非读操作或中止非读操作来实现的。 代码从非易失性可写存储器读取并提供给处理器。 随后，非读取操作在停止的位置恢复，或重新启动。

    User selectable word/byte input architecture for flash EEPROM memory write and erase operations
    8.
    发明授权
    User selectable word/byte input architecture for flash EEPROM memory write and erase operations 失效
    用户可选择的字/字节输入架构，用于闪存EEPROM存储器的写入和擦除操作

    公开(公告)号：US5379413A

    公开(公告)日：1995-01-03

    申请号：US901396

    申请日：1992-06-19

    申请人： Peter K. Hazen ,  Sanjay S. Talreja ,  Rodney R. Rozman

    发明人： Peter K. Hazen ,  Sanjay S. Talreja ,  Rodney R. Rozman

    IPC分类号： G11C7/10 ,  G11C29/38 ,  G06F11/00

    CPC分类号： G11C29/38 ,  G11C7/1006

    摘要： A circuit for accessing data which may be stored in a flash EEPROM memory array in sixteen bit quantities has apparatus for writing data to the array in eight bit quantities which quantities may be either the lower or upper byte of a word and appear at identical input terminals, apparatus for writing data to the array in sixteen bit quantities, apparatus for reading data from the array to identical output terminals in eight bit quantities which quantities may be either the lower or upper byte of a word, and apparatus for reading data from the array in sixteen bit quantities. The circuit also has apparatus for reading data from the array in eight and sixteen bit quantities during periods in which an erase operation conducted on sixteen bits is suspended.

    摘要翻译： 用于以十六位数存储在快闪EEPROM存储器阵列中的数据访问电路具有用于以八位数将数据写入阵列的装置，该数量可以是字的较低或高字节，并出现在相同的输入端 用于以十六位数据将数据写入阵列的装置，用于以八位数量从阵列读取数据到相同输出端的装置，该数量可以是字的较低或高字节，以及用于从阵列读取数据的装置 十六位数。 电路还具有用于在暂停执行16位擦除操作的周期期间以8位和16位数据从阵列读取数据的装置。

    Nonvolatile writeable memory with preemption pin
    9.
    发明授权
    Nonvolatile writeable memory with preemption pin 失效
    具有抢占引脚的非易失性可写存储器

    公开(公告)号：US06201739B1

    公开(公告)日：2001-03-13

    申请号：US08717214

    申请日：1996-09-20

    申请人： Charles W. Brown ,  Peter K. Hazen

    发明人： Charles W. Brown ,  Peter K. Hazen

    IPC分类号： G11C1604

    CPC分类号： G06F9/4406 ,  G06F9/4403 ,  G06F9/44573 ,  G11C16/16 ,  G11C2216/20

    摘要： A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.

    摘要翻译： 使用引脚执行用于抢占非易失性可写存储器中的操作的方法和装置。 通过暂停操作或中止操作来实现操作。 一旦在非易失性可写存储器中暂停操作，则可以执行其他操作。 随后可以恢复暂停的操作。