公开(公告)号：US08415227B2

公开(公告)日：2013-04-09

申请号：US13220460

申请日：2011-08-29

申请人： Sandra Malhotra ,  Wim Deweerd ,  Hanhong Chen ,  Xiangxin Rui ,  Hiroyuki Ode ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi

发明人： Sandra Malhotra ,  Wim Deweerd ,  Hanhong Chen ,  Xiangxin Rui ,  Hiroyuki Ode ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi

IPC分类号： H01L21/20 ,  H01L21/31

CPC分类号： H01L28/60 ,  H01L28/40 ,  H01L28/75

摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

公开(公告)号：US20130052792A1

公开(公告)日：2013-02-28

申请号：US13220460

申请日：2011-08-29

申请人： Sandra Malhotra ,  Wim Deweerd ,  Hanhong Chen ,  Xiangxin Rui ,  Hiroyuki Ode ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi

发明人： Sandra Malhotra ,  Wim Deweerd ,  Hanhong Chen ,  Xiangxin Rui ,  Hiroyuki Ode ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L28/40 ,  H01L28/75

摘要： A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

摘要翻译： 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

公开(公告)号：US20070148896A1

公开(公告)日：2007-06-28

申请号：US11563442

申请日：2006-11-27

申请人： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

发明人： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

IPC分类号： H01L21/20

CPC分类号： H01L28/65 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10852

摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

摘要翻译： 一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件 经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。 下部电极的底部的厚度为30nm以上。 具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

公开(公告)号：US07224016B2

公开(公告)日：2007-05-29

申请号：US10777704

申请日：2004-02-13

申请人： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

发明人： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

IPC分类号： H01L21/8242

CPC分类号： H01L28/65 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10852

摘要： A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

摘要翻译： 一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件 经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。 下部电极的底部的厚度为30nm以上。 具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

公开(公告)号：US08026184B2

公开(公告)日：2011-09-27

申请号：US11965840

申请日：2007-12-28

申请人： Mitsuhiro Horikawa

发明人： Mitsuhiro Horikawa

IPC分类号： H01L29/72

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： Disclosed is a method of manufacturing a semiconductor device formed by laminating a capacitor including a bottom metal electrode, a capacitive insulating film, and an upper metal electrode. When the capacitive insulating film is formed by performing a first step of forming a first dielectric layer on the bottom metal electrode by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric; and a second step of forming a second dielectric layer on the first dielectric layer by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric, a film forming temperature in the first step is set so as to be lower than a film forming temperature in the second step.

摘要翻译： 公开了一种通过层叠包括底部金属电极，电容绝缘膜和上部金属电极的电容器形成的半导体器件的制造方法。 当通过使用包含电介质的构成元素的前体气体的气相成膜方法进行在底部金属电极上形成第一电介质层的第一步骤而形成电容绝缘膜时; 以及通过使用包含电介质的构成元素的前体气体的气相成膜法在第一介电层上形成第二电介质层的第二工序，将第一工序中的成膜温度设定为低于 第二步中的成膜温度。

公开(公告)号：US07790613B2

公开(公告)日：2010-09-07

申请号：US12021113

申请日：2008-01-28

申请人： Mitsuhiro Horikawa

发明人： Mitsuhiro Horikawa

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/40

摘要： A semiconductor device includes: a semiconductor substrate; a memory cell selection transistor that is formed on the semiconductor substrate and has a source and a drain; a contact plug; a polysilicon interlayer film that is formed above the memory cell selection transistor and has a cylinder-shaped through-hole; and a storage capacity part that is formed in the through-hole and is connected to the source and the drain of the memory cell selection transistor via the contact plug, wherein a boundary between a bottom and a side wall of the through-hole has a curved surface.

摘要翻译： 半导体器件包括：半导体衬底; 存储单元选择晶体管，其形成在所述半导体基板上并具有源极和漏极; 接触塞 形成在所述存储单元选择晶体管的上方并具有圆筒状的通孔的多晶硅层间膜; 以及存储电容部，其形成在所述通孔中并且经由所述接触插塞连接到所述存储单元选择晶体管的所述源极和漏极，其中，所述通孔的底部和侧壁之间的边界具有 曲面。

公开(公告)号：US6046095A

公开(公告)日：2000-04-04

申请号：US340002

申请日：1999-06-25

申请人： Mitsuhiro Horikawa

发明人： Mitsuhiro Horikawa

IPC分类号： H01L21/322 ,  H01C21/324

CPC分类号： H01L21/3221 ,  Y10S257/913

摘要： On the back side of a base body, three layers of polysilicon layer are formed. These polysilicon layers contain boron. A boron concentration C.sub.B(1), C.sub.B(2) and C.sub.B(3) of the first, second and third polysilicon layers from the base body side have a relationship of C.sub.B(1) .ltoreq.C.sub.B(2) .ltoreq.C.sub.B(3). On the other hand, between the polysilicon layers, silicon oxide layers are formed respectively. Upon fabrication of a semiconductor device, at first, a gettering heat treatment is effected for the substrate under a given condition. Thus, contaminating impurity is captured at the grain boundary of polysilicon layers formed on the back side of the base body. Next, the polysilicon formed at the most back side is removed by etching. By this, contaminated impurity is removed from the semiconductor substrate.

摘要翻译： 在基体的背面形成三层多晶硅层。 这些多晶硅层含有硼。 来自基体侧的第一，第二和第三多晶硅层的硼浓度CB（1），CB（2）和CB（3）具有CB（1）

公开(公告)号：US20070155115A1

公开(公告)日：2007-07-05

申请号：US11638497

申请日：2006-12-14

申请人： Mitsuhiro Horikawa

发明人： Mitsuhiro Horikawa

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L21/0214 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/3185 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/84

摘要： A method according to the present invention includes forming a silicon nitride film on a lower electrode, oxidizing the silicon nitride film, and forming a dielectric film including aluminum on the oxidized silicon nitride film.

摘要翻译： 根据本发明的方法包括在下电极上形成氮化硅膜，氧化氮化硅膜，并在氧化的氮化硅膜上形成包含铝的电介质膜。

公开(公告)号：US20090230510A1

公开(公告)日：2009-09-17

申请号：US12400553

申请日：2009-03-09

申请人： Hiroshi Miki ,  Tomoko Sekiguchi ,  Naomi Inada ,  Mitsuhiro Horikawa

发明人： Hiroshi Miki ,  Tomoko Sekiguchi ,  Naomi Inada ,  Mitsuhiro Horikawa

IPC分类号： H01L29/92 ,  H01L21/02 ,  H01L21/31 ,  H01L27/108

CPC分类号： H01L21/02186 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02175 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in capacitance per unit area of a DRAM memory cell and enables a high-integration DRAM to be realized at low cost.

摘要翻译： 即使在0.5〜10atm％的二氧化钛中添加镍或钴，也可以形成金红石相，在电容器用电介质膜中使用该元素添加二氧化钛膜 DRAM存储单元的每单位面积的电容增加，能够以低成本实现高集成度的DRAM。

公开(公告)号：US20090152677A1

公开(公告)日：2009-06-18

申请号：US12292814

申请日：2008-11-26

申请人： Mitsuhiro Horikawa

发明人： Mitsuhiro Horikawa

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10894

摘要： A semiconductor device including: a conducting plug provided in an interlayer insulating film over a semiconductor substrate; and a capacitor including a lower electrode provided over the conducting plug, the lower electrode being connected to the conducting plug, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film. The lower electrode includes a conducting pillar and a conducting outer layer provided over at least a circumferential side surface of the conducting pillar. The dielectric film covers at least a circumferential side surface of the lower electrode, and is contact with the conducting outer layer.

摘要翻译： 一种半导体器件，包括：设置在半导体衬底上的层间绝缘膜中的导电插塞; 以及电容器，包括设置在所述导电插塞上的下电极，所述下电极连接到所述导电插塞，设置在所述下电极上的电介质膜和设置在所述电介质膜上的上电极。 下电极包括导电柱和设置在导电柱的至少周向侧表面上的导电外层。 电介质膜至少覆盖下电极的周向侧面，与导电外层接触。