公开(公告)号：US06221769B1

公开(公告)日：2001-04-24

申请号：US09263031

申请日：1999-03-05

申请人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

发明人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

IPC分类号： H01L2144

CPC分类号： H01L21/486 ,  H01L21/76898 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/00

摘要： A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.

摘要翻译： 一种用于向集成电路硅封装提供贯穿晶片连接的方法。 首先在硅封装中产生一个孔，其中内表面区域从硅封装的底表面延伸到硅封装的顶表面。 孔由两种方法之一创建。 第一个涉及以高速度旋转的钻石钻头的机械钻孔。 第二个涉及使用浆料和钢指的超声波铣削。 孔的内表面积被绝缘材料覆盖，以使稍后沉积的导电材料绝缘并用作扩散阻挡层，然后种子材料放置在孔中。 最后，孔填充有导电材料，该导电材料用于提供大的功率输入或信号连接到集成电路芯片。

公开(公告)号：US6166437A

公开(公告)日：2000-12-26

申请号：US290921

申请日：1999-04-12

申请人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

发明人： Sang Hoo Dhong ,  Kevin John Nowka ,  Michael Jay Shapiro

IPC分类号： H01L23/13 ,  H01L23/544 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/544 ,  H01L23/13 ,  H01L2223/54426 ,  H01L2224/10165 ,  H01L2224/81141 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2224/0401

摘要： A silicon wafer is etched to form a first and second series of guidance features. The features of the first series are larger than and surround the features of the second series. The second series is clustered into groups and a hole is formed in the center of each group. The wafer is designed to integrate a silicon package having preformed contacts with a plurality of silicon-based chips. The package and each chip has a series of guidance recesses which correspond to the guidance features of the first and second series, respectively. One chip is placed on top of each group of the second series, and the package is placed on top of the first series. The recesses in the package and chips will precisely align with and slidingly engage the upper ends of the features. Since the features of the first series are larger than those of the second series, there is a clearance between the package and the chips. In the final stage of assembly, the package is restrained from movement and a pin is inserted through each hole in the wafer to force the chips into contact with the contacts on the package. Heat is then applied to fuse solder balls on the chips with the contacts to form a complete and finished assembly.

摘要翻译： 蚀刻硅晶片以形成第一和第二系列的引导特征。 第一系列的特征大于第二系列的特征并且围绕着第二系列的特征。 第二个系列分组成群，在每组的中心形成一个孔。 晶片被设计成将具有预成型触点的硅封装与多个硅基芯片集成。 封装和每个芯片具有一系列引导凹槽，其分别对应于第一和第二系列的引导特征。 一个芯片放置在第二个系列的每个组的顶部，并且包装被放置在第一系列的顶部。 封装和芯片中的凹槽将精确地对准并滑动地接合特征的上端。 由于第一系列的特征大于第二系列的特征，所以封装和芯片之间存在间隙。 在组装的最后阶段，封装被限制移动，并且销穿过晶片中的每个孔，以迫使芯片与封装上的触点接触。 然后施加热量以使具有触头的芯片上的焊球熔合以形成完整和完成的组件。

公开(公告)号：US06360238B1

公开(公告)日：2002-03-19

申请号：US09270469

申请日：1999-03-15

申请人： Sang Hoo Dhong ,  Kyung Tek Lee ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Kyung Tek Lee ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F501

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936

摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

摘要翻译： 公开了具有集成符号选择器的零/一预测器。 通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。 前导零字符串为正和，前导字符串为负数。 然后从前导零字符串和前导字符串确定归一化偏移量。 然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。 然后，利用该符号来选择正和或负的正和归一化移位量。

公开(公告)号：US06594679B1

公开(公告)日：2003-07-15

申请号：US09531850

申请日：2000-03-20

申请人： Kyung Tek Lee ,  Kevin John Nowka ,  Sang Hoo Dhong

发明人： Kyung Tek Lee ,  Kevin John Nowka ,  Sang Hoo Dhong

IPC分类号： G06F1500

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936 ,  G06F7/5443

摘要： A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.

摘要翻译： 公开了一种具有独立符号位确定模块的前置零预测器。 用于预测浮点处理器内的加法器的前导零的装置包括前置零预测器和符号确定模块。 前导零预测器通过检查进位传播，产生和杀死加法器的两个输入操作数的两个相邻位来产生前导零字符串和前导字符串。 前导零字符串用于正和，并且前导字符串用于负和。 独立于前置零预测器，符号确定模块根据前置零预测器中的操作来确定加法器的输出的符号。

公开(公告)号：US06282557B1

公开(公告)日：2001-08-28

申请号：US09207483

申请日：1998-12-08

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F748

CPC分类号： G06F7/5443 ,  G06F7/5318

摘要： A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.

摘要翻译： 公开了一种用于将第一二进制数和第二二进制数的乘积加到第三个二进制数的低延迟融合乘法加法器。 低延迟融合乘法器包括部分乘积生成模块，部分乘积减少模块和进位传播加法器。 部分乘积生成模块从第一二进制数和第二二进制数生成一组部分乘积。 与部分产品生成模块相结合，部分产品减少模块将部分产品集合与第三个二进制数组合，以产生冗余Sum和冗余进位。 最后，进位传播加法器将冗余Sum和冗余Carry相加，得到Sum Total。

公开(公告)号：US06237085B1

公开(公告)日：2001-05-22

申请号：US09207482

申请日：1998-12-08

申请人： Jeffrey Burns ,  Sang Hoo Dhong ,  Kevin John Nowka

发明人： Jeffrey Burns ,  Sang Hoo Dhong ,  Kevin John Nowka

IPC分类号： G06F9305

CPC分类号： G06F9/30094 ,  G06F7/026 ,  G06F9/3875

摘要： A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two operands. Concurrent with the execution of the arithmetic or logical instruction by the execution resources, the condition code logic determines less than, greater than, and equal to condition code bits associated with the result of the arithmetic or logical instruction. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits. The condition code logic is also capable of receiving externally computed condition code bits associated with complex instructions and utilizing such condition code bits to produce the output signals.

摘要翻译： 处理器包括执行资源和条件代码逻辑。 执行资源通过算术或逻辑地组合至少两个操作数来执行算术或逻辑指令。 与执行资源执行算术或逻辑指令同时，条件代码逻辑确定小于，大于和等于与算术或逻辑指令的结果相关联的条件码位。 在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。 对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。 耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。 条件代码逻辑还能够接收与复杂指令相关联的外部计算的条件码位，并利用这些条件码位产生输出信号。

公开(公告)号：US06345286B1

公开(公告)日：2002-02-05

申请号：US09182593

申请日：1998-10-30

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F750

CPC分类号： G06F7/607 ,  G06F2207/3872

摘要： A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. The first data output is a SUM output, the second data output is a CARRY—2 output, and the third data output is a CARRY—4 output.

摘要翻译： 公开了一种6比3的进位保存二进制加法器。 6对3进位存储加法器包括用于接收六个数据输入的装置和用于同时添加六个数据输入以产生第一数据输出，第二数据输出和第三数据输出的装置。 第一个数据输出是一个SUM输出，第二个数据输出是一个CARRY-2输出，第三个数据输出是一个CARRY-4输出。

公开(公告)号：US06212619B1

公开(公告)日：2001-04-03

申请号：US09075918

申请日：1998-05-11

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin John Nowka ,  Joel Abraham Silberman

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Kevin John Nowka ,  Joel Abraham Silberman

IPC分类号： G06F1500

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates a list of tags corresponding to specific registers that are not in use during loading of a given instruction. A table is constructed having one bit for each register per instruction in flight. The entries in the table may be combined in a logical OR fashion to create a vector that identifies which registers are in use by instructions that are in flight. Validity bits can also be generated to indicate validity of the generated tags, wherein a generated tag is invalid only if an insufficient number of registers are available during loading of the given instruction. The execution units are preferably pipelined.

摘要翻译： 一种用于执行无序指令的超标量计算机体系结构，包括多个执行单元，多个寄存器和寄存器重命名电路，该电路生成与给定的加载期间不使用的特定寄存器相对应的标签列表 指令。 在飞行中每个指令的每个寄存器构造一个表。 表中的条目可以以逻辑或或者方式组合，以创建一个向量，用于识别正在飞行中的指令使用哪些寄存器。 也可以生成有效位以指示生成的标签的有效性，其中仅当在给定指令的加载期间没有足够数量的寄存器可用时，所生成的标签才是无效的。 执行单元优选地被流水线化。

公开(公告)号：US06178437B1

公开(公告)日：2001-01-23

申请号：US09139940

申请日：1998-08-25

申请人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

发明人： Sang Hoo Dhong ,  Hung Cai Ngo ,  Kevin John Nowka

IPC分类号： G06F742

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936

摘要： A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.

摘要翻译： 公开了一种用于预测浮点处理器中的前导零/一个的方法。 通过检查两个输入操作数的两个相邻位的进位传播，生成和杀死浮点处理器内的加法器来产生前导零字符串和前导字符串。 前导零字符串为正和，前导字符串为负数。 在确定正和和负的和的输出的符号之前，从前导零字符串和前导字符串直接并发地计算归一化偏移量。

公开(公告)号：US6035390A

公开(公告)日：2000-03-07

申请号：US5471

申请日：1998-01-12

申请人： Jeffrey L. Burns ,  Sang Hoo Dhong ,  Kevin John Nowka ,  Joel Abraham Silberman

发明人： Jeffrey L. Burns ,  Sang Hoo Dhong ,  Kevin John Nowka ,  Joel Abraham Silberman

IPC分类号： G06F9/38 ,  G06F7/48 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/30

CPC分类号： G06F9/3001 ,  G06F7/48 ,  G06F9/30094

摘要： A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.

摘要翻译： 处理器至少包括一个执行单元，该执行单元通过使用一个或多个操作数和条件代码逻辑执行指令所指示的操作来执行指令，所述操作数和条件代码逻辑确定小于，大于和等于与执行同时执行的指令相关联的条件代码位 的执行单元的指令。 在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。 对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。 耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。