公开(公告)号：US20130227884A1

公开(公告)日：2013-09-05

申请号：US13884409

申请日：2011-10-27

申请人： Chul Hong Park ,  Jae Hong Kim ,  Young Hwan Yun ,  Sang Min Kim

发明人： Chul Hong Park ,  Jae Hong Kim ,  Young Hwan Yun ,  Sang Min Kim

IPC分类号： A01G9/02

CPC分类号： A01G9/025 ,  B01D53/84 ,  B01D2258/06 ,  B01D2259/4508 ,  Y02A50/2358 ,  Y02P60/244

摘要： Disclosed is a port for a vertical wall, a multi-filter used therein, and a port support frame. In the port a cover is installed in a port body having an interior space. A plurality of body filter holes penetrate the port body. Soil in which plants are set is filled in the interior space. A plurality of vegetation holes through which the plants set in the soil are formed in the cover, and cover filter holes are formed between the vegetation holes at locations corresponding to the body filter holes. Multi-filters penetrate the body filter holes, the cover filter holes, and the soil. A support tubular body forms an outer appearance of the multi-filter, and a filtering case is installed in the support tubular body.

摘要翻译： 公开了一种用于垂直壁的端口，其中使用的多过滤器和端口支撑框架。 在端口中，盖子安装在具有内部空间的端口体中。 多个主体过滤孔穿透端口主体。 设置植物的土壤填充在内部空间中。 植物在土壤中形成多个植被孔，盖子上形成有与过滤孔对应的位置的植被孔之间的过滤孔。 多过滤器穿透身体过滤孔，盖过滤孔和土壤。 支撑管体形成多过滤器的外观，并且过滤壳体安装在支撑管体中。

公开(公告)号：US08026547B2

公开(公告)日：2011-09-27

申请号：US12417341

申请日：2009-04-02

申请人： Sang Min Kim

发明人： Sang Min Kim

IPC分类号： H01L29/66

CPC分类号： H01L27/11521 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns. First and second conductive pads extend in different directions and are connected to the contact plugs. First and second pad contact plugs are formed on extended peripheries of the first and second conductive pads, respectively. Each of the first pad contact plugs has a height which differs from a height of each of the second pad contact plugs. First bit lines are connected to the first pad contact plugs, and second bit lines are connected to the second pad contact plugs.

摘要翻译： 半导体存储器件具有不相对的相邻位线的侧表面，以减小在相邻位线之间形成的寄生电容器的电容。 半导体存储器件包括形成在半导体衬底上的接触插塞。 每个接触插头设置在栅极图案之间。 第一和第二导电焊盘在不同的方向上延伸并连接到接触插头。 第一和第二焊盘接触插塞分别形成在第一和第二导电焊盘的延伸的外围。 每个第一焊盘接触插塞具有与每个第二焊盘接触插塞的高度不同的高度。 第一位线连接到第一焊盘触点插头，第二位线连接到第二焊盘触点插头。

公开(公告)号：US20080292696A1

公开(公告)日：2008-11-27

申请号：US10598122

申请日：2006-04-28

申请人： Sang Min Kim ,  Woo Heon Song

发明人： Sang Min Kim ,  Woo Heon Song

IPC分类号： A61K9/24 ,  A61K31/4525

CPC分类号： A61K9/2886 ,  A61K9/2054 ,  A61K9/2846 ,  A61K9/2866

摘要： The present invention relates to an enteric, sustained-release tablet comprising paroxetine or a hydrates or anhydrides of a pharmaceutically acceptable salt thereof as active substance, more particularly to a tablet prepared by coating a sustained-release tablet core containing paroxetine with an enteric polymer, wherein the interaction between the tablet core and the enteric coating layer is minimized to enable constant drug release without regard to the residence time of the tablet in the stomach.

摘要翻译： 本发明涉及包含帕罗西汀或其药学上可接受的盐的水合物或酸酐作为活性物质的肠溶缓释片剂，更具体地涉及通过用肠溶性聚合物涂布含有帕罗西汀的缓释片剂芯片， 其中所述片芯和所述肠溶衣层之间的相互作用被最小化，以使药物不断释放，而不考虑片剂在胃中的停留时间。

公开(公告)号：US20080280431A1

公开(公告)日：2008-11-13

申请号：US11955349

申请日：2007-12-12

申请人： Woo Yung Jung ,  Choi Dong Kim ,  Sang Min Kim

发明人： Woo Yung Jung ,  Choi Dong Kim ,  Sang Min Kim

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/942

摘要： The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less.

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 在根据本发明的一个方面的方法中，在半导体层叠体上形成第一硬掩模膜。 通过蚀刻用于硬掩模的绝缘层来形成多个第一硬掩模图案。 间隔件形成在多个第一硬掩模图案的顶表面和侧壁上。 在包括间隔物的整个表面上形成第二硬掩模膜。 通过执行蚀刻工艺在间隔物之间​​的空间中形成第二硬掩模图案，使得间隔物的顶表面露出。 去除间隔物。 因此，可以通过采用具有曝光设备分辨率或更小的间距的硬掩模图案来形成栅极图案。

公开(公告)号：US07696076B2

公开(公告)日：2010-04-13

申请号：US11955349

申请日：2007-12-12

申请人： Woo Yung Jung ,  Choi Dong Kim ,  Sang Min Kim

发明人： Woo Yung Jung ,  Choi Dong Kim ,  Sang Min Kim

IPC分类号： H01L21/31

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/942

摘要： The present invention relates to a method of fabricating a flash memory device. In a method according to an aspect of the present invention, a first hard mask film is formed over a semiconductor laminate. A plurality of first hard mask patterns are formed by etching an insulating layer for a hard mask. Spacers are formed on top surfaces and sidewalls of the plurality of first hard mask patterns. A second hard mask film is formed over a total surface including the spacers. Second hard mask patterns are formed in spaces between the spacers by performing an etch process so that a top surface of the spacers is exposed. The spacers are removed. Accordingly, gate patterns can be formed by employing hard mask patterns having a pitch of exposure equipment resolutions or less.

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 在根据本发明的一个方面的方法中，在半导体层叠体上形成第一硬掩模膜。 通过蚀刻用于硬掩模的绝缘层来形成多个第一硬掩模图案。 间隔件形成在多个第一硬掩模图案的顶表面和侧壁上。 在包括间隔物的整个表面上形成第二硬掩模膜。 通过执行蚀刻工艺在间隔物之间​​的空间中形成第二硬掩模图案，使得间隔物的顶表面露出。 去除间隔物。 因此，可以通过采用具有曝光设备分辨率或更小的间距的硬掩模图案来形成栅极图案。

公开(公告)号：US10925291B2

公开(公告)日：2021-02-23

申请号：US16157513

申请日：2018-10-11

申请人： Youn Je Chun ,  Sang Min Kim

发明人： Won ho Kang ,  Sang Min Kim

IPC分类号： A23B4/16 ,  A23B7/148 ,  A23L13/70 ,  F26B21/14 ,  A23L3/3418 ,  A23B4/06 ,  F26B21/08 ,  A23L3/36 ,  A23B4/08 ,  F26B5/04 ,  A23L3/40 ,  A23B4/037 ,  A23B4/09

摘要： Provided is a dry aging system using oxygen in which a separate dry-aging room is provided in a refrigerating compartment, and a mixed gas using oxygen is supplied into the dry-aging room so as to solve a blacking and browning phenomenon of a meat surface, which is led to an increase in loss rate and an increase in edible meat cost, which are disadvantages of existing dry-aging, thereby allowing the meat surface to be maintained in a bright red color through meat color fixation, minimizing the occurrence of the blacking and browning phenomenon to reduce the loss rate of the edible meat, and supplying flavorful dry-aged meat at a more reasonable price. Also, the blacking and browning phenomenon occurring on the generally dry-aged meat may be significantly reduced to produce aesthetically and tastefully very superior dry-aged meat.

公开(公告)号：US20140330055A1

公开(公告)日：2014-11-06

申请号：US14345501

申请日：2012-09-19

申请人： Ju Dong Lee ,  Kyung Chan Kang ,  Sang Yeon Hong ,  Jae Il Lim ,  Sang Yup Jang ,  Seung Beom Hong ,  Kyeong Ho Kim ,  Kwan Ta Woo ,  Sang Min Kim

发明人： Ju Dong Lee ,  Kyung Chan Kang ,  Sang Yeon Hong ,  Jae Il Lim ,  Sang Yup Jang ,  Seung Beom Hong ,  Kyeong Ho Kim ,  Kwan Ta Woo ,  Sang Min Kim

IPC分类号： C10L3/10

CPC分类号： C10L3/108 ,  B01F7/00158 ,  B01F7/00166 ,  B01F7/00175 ,  B01F7/00208 ,  B01F7/166 ,  B01J4/004 ,  B01J10/00 ,  B01J19/0066 ,  B01J19/18 ,  B01J2219/00094

摘要： The present invention relates to an apparatus comprising a reactor body to which gas and water are supplied to create a gas hydrate; an upper cover which is engaged to an upper portion of the reactor body, a scraper mounted rotationally within the reactor body, and a motor for providing a driving force to the scraper. It is possible to remove gas hydrate particles attached to at least one of an inner surface of the reactor body and an inner surface of the upper cover, by a rotary driving of the scraper. According to the invention, it is possible to prevent a material hindering a heat transfer by attaching on a wall surface of the reactor, through a process of scraping out gas hydrate particles, when the scraper which is rotationally driven about a center axis of the reactor is close to the inner surface of the reactor.

摘要翻译： 本发明涉及包括反应器主体的设备，气体和水被供应到反应器主体以产生气体水合物; 接合到反应器主体的上部的上盖，旋转地安装在反应器主体内的刮刀和用于向刮刀提供驱动力的马达。 通过刮刀的旋转驱动，可以除去附着在反应器主体的内表面和上盖的内表面中的至少一个上的气体水合物颗粒。 根据本发明，当围绕反应器的中心轴旋转驱动的刮刀时，可以通过刮掉气体水合物颗粒的过程来防止阻碍热传递的材料通过附着在反应器的壁表面上 靠近反应堆的内表面。

公开(公告)号：US20130078521A1

公开(公告)日：2013-03-28

申请号：US13314073

申请日：2011-12-07

申请人： Dong Gun Kim ,  Sa Heum Kim ,  Young Jun Kim ,  Jun Ho Song ,  Woo Suk Cho ,  Jeom Soo Kim ,  Sang Min Kim

发明人： Dong Gun Kim ,  Sa Heum Kim ,  Young Jun Kim ,  Jun Ho Song ,  Woo Suk Cho ,  Jeom Soo Kim ,  Sang Min Kim

IPC分类号： H01M4/505 ,  B05D5/12 ,  H01M4/58 ,  H01M4/04 ,  B82Y99/00

CPC分类号： H01M4/136 ,  H01M4/366 ,  H01M4/5825 ,  H01M4/625 ,  H01M10/052 ,  Y02E60/122 ,  Y02P70/54

摘要： Disclosed are compositions and methods for producing a cathode for a secondary battery, where a fluorophosphate of the formula LixNa2-xMnPO4F is used as an electrode material. LixNa2-xMnPO4F is prepared by partially substituting a sodium site with lithium through a chemical method. LixNa2-xMnPO4F prepared according to the invention provides a cathode material for a lithium battery that has improved electrochemical activity.

摘要翻译： 公开了用于生产二次电池阴极的组合物和方法，其中使用式LixNa2-xMnPO4F的氟磷酸盐作为电极材料。 LixNa2-xMnPO4F通过化学方法用锂部分取代钠的部位制备。 根据本发明制备的LixNa2-xMnPO4F提供了具有改善的电化学活性的用于锂电池的阴极材料。

公开(公告)号：US08273652B2

公开(公告)日：2012-09-25

申请号：US13246726

申请日：2011-09-27

申请人： Sang Min Kim

发明人： Sang Min Kim

IPC分类号： H01L21/4763

CPC分类号： H01L27/11521 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes providing a substrate having junction regions and contact plugs formed thereon. A second insulating layer is formed over a first insulating layer and includes first and second pad holes extending in different directions and exposing the contact plugs. First and second conductive pads are formed in the first and second pad holes, respectively. A third insulating layer is formed and includes dual damascene patterns and pad contact holes. The dual damascene pattern exposes the first conductive pad, and each pad contact hole exposes a second conductive pad. First pad contact plugs and a first bit line are formed in the dual damascene pattern and a second pad contact plug is formed in each pad contact hole. A fourth insulating layer including trenches is formed. Each trench exposes a second pad contact plug. A second bit line is formed in each trench.

摘要翻译： 制造半导体器件的方法包括提供具有形成在其上的接合区域和接触插塞的衬底。 第二绝缘层形成在第一绝缘层之上，并且包括沿不同方向延伸并暴露接触插塞的第一和第二焊盘孔。 第一和第二导电焊盘分别形成在第一和第二焊盘孔中。 形成第三绝缘层，并且包括双镶嵌图案和焊盘接触孔。 双镶嵌图案暴露第一导电焊盘，并且每个焊盘接触孔暴露第二导电焊盘。 在双镶嵌图案中形成第一垫接触塞和第一位线，并且在每个垫接触孔中形成第二垫接触塞。 形成包括沟槽的第四绝缘层。 每个沟槽露出第二垫接触插头。 在每个沟槽中形成第二位线。

公开(公告)号：US20090250743A1

公开(公告)日：2009-10-08

申请号：US12417341

申请日：2009-04-02

申请人： Sang Min Kim

发明人： Sang Min Kim

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11521 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns. First and second conductive pads extend in different directions and are connected to the contact plugs. First and second pad contact plugs are formed on extended peripheries of the first and second conductive pads, respectively. Each of the first pad contact plugs has a height which differs from a height of each of the second pad contact plugs. First bit lines are connected to the first pad contact plugs, and second bit lines are connected to the second pad contact plugs.

摘要翻译： 半导体存储器件具有不相对的相邻位线的侧表面，以减小在相邻位线之间形成的寄生电容器的电容。 半导体存储器件包括形成在半导体衬底上的接触插塞。 每个接触插头设置在栅极图案之间。 第一和第二导电焊盘在不同的方向上延伸并连接到接触插头。 第一和第二焊盘接触插塞分别形成在第一和第二导电焊盘的延伸的外围。 每个第一焊盘接触插塞具有与每个第二焊盘接触插塞的高度不同的高度。 第一位线连接到第一焊盘触点插头，第二位线连接到第二焊盘触点插头。