公开(公告)号：US20150187946A1

公开(公告)日：2015-07-02

申请号：US14455036

申请日：2014-08-08

申请人： Sang-Jine PARK ,  Bo-Un YOON ,  Ha-Young JEON ,  Byung-Kwon CHO ,  Jeong-Nam HAN

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Ha-Young JEON ,  Byung-Kwon CHO ,  Jeong-Nam HAN

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

摘要翻译： 半导体器件包括限定沟槽的栅极间隔。 沟槽包括顺序地位于基板上的第一部分和第二部分。 第一部分的内表面具有锐角的斜面，并且第二部分的内表面具有相对于基底的直角或钝角的斜率。 栅电极填充沟槽的至少一部分。

公开(公告)号：US20160268414A1

公开(公告)日：2016-09-15

申请号：US15000495

申请日：2016-01-19

申请人： Sang-Jine PARK ,  Keun-Hee BAI ,  Kyoung-Hwan YEO ,  Bo-Un YOON ,  Kee-Sang KWON ,  Do-Hyoung KIM ,  Ha-Young JEON ,  Seung-Seok HA

发明人： Sang-Jine PARK ,  Keun-Hee BAI ,  Kyoung-Hwan YEO ,  Bo-Un YOON ,  Kee-Sang KWON ,  Do-Hyoung KIM ,  Ha-Young JEON ,  Seung-Seok HA

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L29/785 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/7848

摘要： Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

摘要翻译： 提供了半导体器件，其包括在垂直于第一方向的第二方向上沿第一方向延伸的第一有源鳍片和与第一有源鳍片间隔开的第二有源鳍片，第二有源鳍片沿第一方向延伸，第二有源鳍片 具有比第一活性翅片的长边的长度短的长边。 第一伪栅极在第二方向上延伸，与第一和第二活性鳍片中的每一个的第一端重叠。 第一金属栅极在与第一有效鳍交叉的第二方向上延伸并与第二活动鳍片的第二端重叠。 第一绝缘栅极在与第一活性鳍相交的第二方向上延伸。 第一绝缘栅延伸到第一活性鳍。

公开(公告)号：US20140231010A1

公开(公告)日：2014-08-21

申请号：US14183994

申请日：2014-02-19

申请人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

IPC分类号： H01L21/67

CPC分类号： H01L21/67075 ,  H01L21/67017 ,  H01L21/6708

摘要： A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

摘要翻译： 化学品供应商包括在室温下含有化学混合物的化学容器，化学容器的内部空间与周围环境分离，供应管线，化学混合物通过该供应管线从化学容器供应到处理室，一体式加热器 定位在供应管线上并将供应管线中的化学混合物加热至处理温度，以及驱动化学混合物以将化学混合物移向处理室的电源。

公开(公告)号：US20130023100A1

公开(公告)日：2013-01-24

申请号：US13479679

申请日：2012-05-24

申请人： Sang-Jine PARK ,  Doo-Sung YUN ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Won-Sang CHOI

发明人： Sang-Jine PARK ,  Doo-Sung YUN ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Won-Sang CHOI

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上形成包括栅极和源极和漏极区的晶体管，在所述晶体管上形成层间绝缘膜，在所述层间绝缘膜中形成接触孔以暴露出 源极和漏极区域的顶表面，并且在接触孔和源极和漏极区域的暴露顶表面之间的界面处形成薄膜。 该方法还包括通过在非等离子体气氛中进行蚀刻工艺来选择性地去除薄膜的至少一部分，在选择性地去除薄膜的至少一部分的源区和漏区上形成欧姆接触膜， 以及通过用导电材料填充接触孔来形成接触塞。

公开(公告)号：US20160315045A1

公开(公告)日：2016-10-27

申请号：US15016376

申请日：2016-02-05

申请人： Jae-Jik BAEK ,  Kee-Sang KWON ,  Sang-Jine PARK ,  Bo-Un YOON

发明人： Jae-Jik BAEK ,  Kee-Sang KWON ,  Sang-Jine PARK ,  Bo-Un YOON

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088

CPC分类号： H01L23/528 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0886

摘要： The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

摘要翻译： 半导体器件可以在衬底上包括绝缘中间层，衬底包括其上部的接触区域，穿过绝缘中间层并接触接触区域的主接触插塞，具有柱形形状的主接触插塞包括 第一屏障图案和第一金属图案，以及围绕主接触插塞的上侧壁的延伸图案，延伸图案包括阻挡材料。 在半导体器件中，接触结构和其上的布线之间的对准边缘可能增加。 此外，可以减小接触结构和栅电极之间的短路故障。