公开(公告)号：US09755079B2

公开(公告)日：2017-09-05

申请号：US15000495

申请日：2016-01-19

申请人： Sang-Jine Park ,  Keun-Hee Bai ,  Kyoung-Hwan Yeo ,  Bo-Un Yoon ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Ha-Young Jeon ,  Seung-Seok Ha

发明人： Sang-Jine Park ,  Keun-Hee Bai ,  Kyoung-Hwan Yeo ,  Bo-Un Yoon ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Ha-Young Jeon ,  Seung-Seok Ha

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/7848

摘要： Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

公开(公告)号：US09748234B2

公开(公告)日：2017-08-29

申请号：US14826811

申请日：2015-08-14

申请人： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

发明人： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

摘要： Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US20160163718A1

公开(公告)日：2016-06-09

申请号：US15047181

申请日：2016-02-18

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L27/11 ,  H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20130115759A1

公开(公告)日：2013-05-09

申请号：US13561245

申请日：2012-07-30

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/20

CPC分类号： H01L29/66636 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/78 ,  H01L29/7848

摘要： Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.

摘要翻译： 提供制造半导体器件的方法，其包括提供包括具有栅极图案的第一区域和具有填充第一沟槽的第一沟槽和绝缘层的第二区域的衬底。 通过蚀刻绝缘层的一部分露出第一沟槽的侧壁的一部分，并且在栅极图案的侧壁上形成第一间隔物。 第二间隔件形成在第一沟槽的暴露的侧壁上，其中第一间隔件和第二间隔件同时形成。

公开(公告)号：US20140231010A1

公开(公告)日：2014-08-21

申请号：US14183994

申请日：2014-02-19

申请人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

IPC分类号： H01L21/67

CPC分类号： H01L21/67075 ,  H01L21/67017 ,  H01L21/6708

摘要： A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

摘要翻译： 化学品供应商包括在室温下含有化学混合物的化学容器，化学容器的内部空间与周围环境分离，供应管线，化学混合物通过该供应管线从化学容器供应到处理室，一体式加热器 定位在供应管线上并将供应管线中的化学混合物加热至处理温度，以及驱动化学混合物以将化学混合物移向处理室的电源。

公开(公告)号：US08709942B2

公开(公告)日：2014-04-29

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US20130023119A1

公开(公告)日：2013-01-24

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US10128236B2

公开(公告)日：2018-11-13

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L29/772 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US20160284806A1

公开(公告)日：2016-09-29

申请号：US14989485

申请日：2016-01-06

申请人： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

发明人： Sangjine Park ,  Kee Sang Kwon ,  Jae-Jik Baek ,  Boun Yoon

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L23/31 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/785

摘要： A semiconductor device includes an active pattern protruding from a substrate, gate structures crossing over the active pattern, gate spacers on sidewalls of the gate structures, a source/drain region n the active pattern between the gate structures, and a source/drain contact on and connected to the source/drain region. The source/drain contact includes a first portion between the gate structures and being in contact with the gate spacers, a second portion on the first portion and not being in contact with the gate spacers, and a third portion on the second portion. A first boundary between the second and third portions is at the substantially same height as a top surface of the gate structure.

摘要翻译： 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构，栅极结构的侧壁上的栅极间隔物，栅极结构之间的有源图案的源极/漏极区域以及栅极结构之间的源极/漏极接触 并连接到源极/漏极区域。 源极/漏极接触包括在栅极结构之间并与栅极间隔物接触的第一部分，第一部分上的第二部分并且不与栅极间隔物接触，并且在第二部分上具有第三部分。 第二和第三部分之间的第一边界处于与栅极结构的顶表面基本相同的高度。

公开(公告)号：US20160064378A1

公开(公告)日：2016-03-03

申请号：US14826811

申请日：2015-08-14

申请人： Kee Sang KWON ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

发明人： Kee Sang KWON ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

摘要： Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

摘要翻译： 半导体器件可以包括衬底，衬底上的栅极电极以及每个栅极电极的两侧的源极/漏极区域。 每个栅极电极可以包括在基板上的栅极绝缘图案，位于栅极绝缘图案上并具有凹陷的上表面的下部功函电极图案和在凹陷部分上保形延伸的上部功函电极图案 下工作电极图案的上表面。 下部功函电极图案的最表面可以设置在相同的水平，并且上部功函电极图案可以具有彼此不同的厚度。