公开(公告)号：US20130170297A1

公开(公告)日：2013-07-04

申请号：US13619118

申请日：2012-09-14

申请人： Sang-Wan NAM ,  Kyung-Hwa KANG ,  Junghoon PARK

发明人： Sang-Wan NAM ,  Kyung-Hwa KANG ,  Junghoon PARK

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11582

摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.

摘要翻译： 根据示例性实施例，非易失性存储器件包括第一和第二NAND串。 第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。 第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。 该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。 第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

公开(公告)号：US20130250677A1

公开(公告)日：2013-09-26

申请号：US13661021

申请日：2012-10-25

申请人： Sang-Wan NAM ,  Junghoon PARK

发明人： Sang-Wan NAM ,  Junghoon PARK

IPC分类号： G11C16/10

CPC分类号： G11C13/0002 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C2211/5648 ,  G11C2213/71

摘要： Disclosed is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line.

摘要翻译： 公开了一种用于编程非易失性存储器件的方法，其包括以多行排列的存储器单元。 编程方法包括交替地选择字线以在与存储器单元相关联的第一页部分处编程数据和第二页面部分。 在第一和第二页面部分被编程之后，该方法包括根据排列字线的顺序在与存储器单元相关联的第三页部分处编程数据。 字线可以从与地选择线相邻的字线逐个地依次选择。

公开(公告)号：US20180122695A1

公开(公告)日：2018-05-03

申请号：US15857961

申请日：2017-12-29

申请人： Dohyun LEE ,  Youngwoo PARK ,  Junghoon PARK ,  Jaeduk LEE

发明人： Dohyun LEE ,  Youngwoo PARK ,  Junghoon PARK ,  Jaeduk LEE

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US20130022486A1

公开(公告)日：2013-01-24

申请号：US13555385

申请日：2012-07-23

申请人： Junghoon PARK ,  Sungsoon Jang ,  Jeonghun Kim ,  Nara Han

发明人： Junghoon PARK ,  Sungsoon Jang ,  Jeonghun Kim ,  Nara Han

IPC分类号： F01C1/02

CPC分类号： F04C18/0261 ,  F04C18/0215 ,  F04C23/008 ,  F04C28/26 ,  F04C28/28

摘要： A scroll compressor is provided, in which at least one bypass hole that bypass a portion of a refrigerant before the refrigerant is discharged through a discharge hole is formed at a position where a bypass section that bypasses the refrigerant through the at least one bypass hole overlaps a discharge section that discharges the refrigerant through the discharge hole. The at least one bypass hole is formed at a position where a wrap volume ratio (Vs/Vd), which is a ratio of a suction volume (Vs) with respect to a discharge volume (Vd) in a compression chamber, is within the range of about 1.8˜2.2. With this configuration, over-compression of refrigerant may be prevented in a low speed driving mode, and efficiency of the compressor may be enhanced in the low speed driving mode and under a low load condition.

摘要翻译： 提供了一种涡旋式压缩机，其中在通过所述至少一个旁通孔旁路制冷剂的旁通部分的位置处形成有至少一个在制冷剂通过排出孔排出之前绕过制冷剂的一部分的旁通孔重叠 排出部，其通过排出孔排出制冷剂。 至少一个旁通孔形成在作为吸入容积（Vs）相对于压缩室中的排出容积（Vd）的比率的卷绕体积比（Vs / Vd）在 范围约1.8〜2.2。 利用这种结构，可以在低速驱动模式下防止制冷剂的过度压缩，并且在低速驱动模式和低负载条件下可以提高压缩机的效率。