Pre-ligand assembly domain of the IL-17 receptor
    1.
    发明授权
    Pre-ligand assembly domain of the IL-17 receptor 失效
    IL-17受体的前配体组装结构域

    公开(公告)号:US08460647B2

    公开(公告)日:2013-06-11

    申请号:US12595585

    申请日:2008-04-20

    摘要: The invention provides isolated Pre-Ligand Assembly Domain (PLAD) polypeptides comprising an amino acid sequence of a domain (e.g., a Fibronectin Ill-like domain) of an IL-17 Receptor (IL-17R) family member, wherein the PLAD polypeptide inhibits multimerization of a receptor complex comprising an IL-17R family member. Also provided are isolated PLAD-binding polypeptides, e.g., antibodies and avimers, which specifically bind to a PLAD polypeptide described herein. Related chimeric proteins, conjugates, nucleic acids, vectors, and host cells are provided herein. Further provided are methods of treating an inflammatory or autoimmune disease, methods of inhibiting IL-17-mediated signal transduction, methods of inhibiting IL-17 ligand binding, methods of inhibiting multimerization of IL-17R complexes, and methods of inhibiting the production of at least one cytokine, chemokine, matrix metalloproteinase, or other molecule associated with IL-17 signal transduction are provided.

    摘要翻译: 本发明提供了包含IL-17受体(IL-17R)家族成员的结构域(例如,纤连蛋白III样结构域)的氨基酸序列的分离的前配体组装域(PLAD)多肽,其中PLAD多肽抑制 包含IL-17R家族成员的受体复合物的多聚化。 还提供了分离的PLAD结合多肽,例如特异性结合本文所述的PLAD多肽的抗体和avim。 本文提供了相关嵌合蛋白,缀合物,核酸,载体和宿主细胞。 还提供了治疗炎性或自身免疫性疾病的方法,抑制IL-17介导的信号转导的方法,抑制IL-17配体结合的方法,抑制IL-17R复合物多聚化的方法,以及抑制IL-17介导的信号转导的方法 提供了至少一种细胞因子,趋化因子,基质金属蛋白酶或与IL-17信号转导相关的其它分子。

    Circuit and method for reducing lock-in time in phase-locked and
delay-locked loops
    4.
    发明授权
    Circuit and method for reducing lock-in time in phase-locked and delay-locked loops 失效
    用于减少锁相和延迟锁定环路中锁定时间的电路和方法

    公开(公告)号:US06031429A

    公开(公告)日:2000-02-29

    申请号:US834550

    申请日:1997-03-19

    申请人: Fang Shen

    发明人: Fang Shen

    摘要: Method and circuit aspects for improving lock-in time following power-up in a phase-locked loop are provided. The circuit and method for providing same includes a phase-locked loop, the phase-locked loop comprising a low pass filter, and a pulse generation circuit coupled to the low pass filter. The pulse generation circuit provides a control pulse of predetermined duration to increase a voltage across the low pass filter and reduce lock-in time in the phase-locked loop following power-up. The pulse generation circuit further includes a plurality of logic gates, the plurality of logic gates including a plurality of inverters coupled to a NAND gate.

    摘要翻译: 提供了用于在锁相环中加电之后改善锁定时间的方法和电路方面。 用于提供它的电路和方法包括锁相环,锁相环包括低通滤波器和耦合到低通滤波器的脉冲发生电路。 脉冲发生电路提供预定持续时间的控制脉冲,以增加低通滤波器上的电压,并减少上电后锁相环中的锁定时间。 所述脉冲发生电路还包括多个逻辑门,所述多个逻辑门包括耦合到NAND门的多个反相器。

    Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal
    5.
    发明授权
    Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal 有权
    延迟锁定环电路,用于使参考信号与输出信号同步的系统和方法

    公开(公告)号:US06242955B1

    公开(公告)日:2001-06-05

    申请号:US09399116

    申请日:1999-09-20

    申请人: Fang Shen Chen Wang

    发明人: Fang Shen Chen Wang

    IPC分类号: H03L706

    摘要: A method and system for synchronizing a reference signal and an output signal produced by an electrical circuit, the electrical circuit comprising an analog portion and a digital portion, is disclosed. The method comprises the steps of utilizing the digital portion to produce a phase-adjusted signal and utilizing the analog portion to produce an output signal in substantially the same phase as the phase-adjusted signal. Through the use of the method and system in accordance with the present invention, the large bi-direction shift register of conventional hybrid DLLs is no longer necessary and high speed DLLs will be capable of providing high resolution deskewed clocks in a shorter amount of time. The use of the present invention also facilitates the coverage of a wider range of clock frequencies.

    摘要翻译: 公开了一种用于同步参考信号和由电路产生的输出信号的方法和系统,该电路包括模拟部分和数字部分。 该方法包括以下步骤:利用数字部分产生相位调整信号,利用模拟部分产生与相位调整信号基本相同的输出信号。 通过使用根据本发明的方法和系统,常规混合DLL的大型双向移位寄存器不再是必需的,并且高速DLL将能够在更短的时间内提供高分辨率的偏移校正时钟。 本发明的使用也有助于更宽范围的时钟频率的覆盖。

    Sulfonyl-containing 3,4-diaryl-3-pyrrolin-2-ones, preparation method, and medical use thereof
    8.
    发明授权
    Sulfonyl-containing 3,4-diaryl-3-pyrrolin-2-ones, preparation method, and medical use thereof 有权
    含磺酰基的3,4-二芳基-3-吡咯啉-2-酮,其制备方法和医疗用途

    公开(公告)号:US07112605B2

    公开(公告)日:2006-09-26

    申请号:US10437804

    申请日:2003-05-14

    IPC分类号: A61K31/4015 C07D207/38

    CPC分类号: C07D207/12

    摘要: The invention relates to sulfonyl-containing 3,4-diaryl-3-pyrrolin-2-ones compounds having formula (I) wherein R1 is selected from the group consisting of 4-methylsulfonyl, 4-aminosulfonyl, hydrogen, 2-, 3-, or 4-halogen, C1–C6-alkyl, cyclopentyl, cyclohexyl, C1–C4-alkoxy, hydroxy, cyano, nitro, amino or trifluoromethyl; R2 is selected from the group consisting of 4-methylsulfonyl, 4-aminosulfonyl, hydrogen, 2-, 3-, or 4-halogen, C1–C6-alkyl, cyclopentyl, cyclohexyl, C1–C4-alkoxy, hydroxy, cyano, nitro, amino or trifluoromethyl; and R3 is selected from the group consisting of hydrogen, methyl, ethyl, n-propyl, i-propyl, c-propyl, n-butyl, isobutyl; provided that when R1 is a methylsulfonyl or aminosulfonyl group, R2 is any group as defined above except a methylsulfonyl or aminosulfonyl group; and when R2 is a methylsulfonyl or aminosulfonyl group, R1 is any group as defined above except a methylsulfonyl or aminosulfonyl group, also to processes for the preparation of such compounds, to pharmaceutical compositions containing such compounds, and to the medical use of such compounds in the treatment of diseases relating to the inhibition of cyclooxygenase-2 (COX-2).

    摘要翻译: 本发明涉及具有式(I)的含磺酰基的3,4-二芳基-3-吡咯啉-2-酮化合物,其中R 1选自4-甲基磺酰基,4-氨基磺酰基 ,氢,2-,3-或4-卤素,C 1 -C 6 - 烷基,环戊基,环己基,C 1〜 C 4 - 烷氧基,羟基,氰基,硝基,氨基或三氟甲基; R 2选自4-甲基磺酰基,4-氨基磺酰基,氢,2-,3-或4-卤素,C 1 -C 6 - 烷基,环戊基,环己基,C