-
公开(公告)号：US20100323835A1
公开(公告)日：2010-12-23
申请号：US12449447
申请日：2008-02-20
IPC分类号： F16G1/00
摘要： A V-ribbed belt 10 includes a bottom rubber layer 12, an adhesive rubber layer 16, and a fabric 22. The bottom rubber layer 12 includes short fibers 14, a part of which protrude from the friction surface 12S of the bottom rubber layer 12. In the bottom rubber layer 12, an FEF carbon black with an average nitrogen adsorption surface area (ASTM D1765-01) of below 49 (m2/g), is used as a reinforcement. Therefore, the friction surface 12S of the bottom rubber layer 12 is slightly uneven, thus preventing the generation of an abnormal noise under usage of the V-ribbed belt 10. Further, after the short fibers 14 protruding from the friction surface 12S of the bottom rubber layer 12 have worn down, the unevenness of the friction surface 12S can be properly maintained by using such a carbon black, so that abnormal noise can be prevented.
摘要翻译： V形肋带10包括底部橡胶层12，粘合橡胶层16和织物22.底部橡胶层12包括短纤维14，其一部分从底部橡胶层12的摩擦表面12S突出 在底部橡胶层12中，使用平均氮吸附表面积（ASTM D1765-01）低于49（m 2 / g）的FEF炭黑作为增强材料。 因此，底部橡胶层12的摩擦面12S稍微不均匀，从而防止在V形带10的使用下产生异常噪音。此外，在短纤维14从底部的摩擦面12S突出后， 橡胶层12已经磨损，可以通过使用这种炭黑适当地保持摩擦表面12S的不均匀性，从而可以防止异常噪音。
-
公开(公告)号：USD569799S1
公开(公告)日：2008-05-27
申请号：US29252035
申请日：2006-01-17
-
公开(公告)号：US6130126A
公开(公告)日：2000-10-10
申请号：US339728
申请日：1999-06-24
申请人： Takashi Iwakiri
发明人： Takashi Iwakiri
IPC分类号： G11C16/04 , H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/82
摘要： The dummy oxide used to form DRAM capacitor cells is left in place over the peripheral transistors, reducing the height difference between the DRAM array and the peripheral circuitry and protecting against edge effects.
摘要翻译： 用于形成DRAM电容器单元的虚拟氧化物留在外围晶体管上，降低了DRAM阵列与外围电路之间的高度差，并且防止边缘效应。
-
4.发明申请Solid-Electrolyte Capacitor, Manufacturing Method Thereof, and Digital Signal Processing Substrate Using the Solid Electrolyte Capacitor 有权固体电解质电容器，其制造方法和使用固体电解质电容器的数字信号处理基板公开(公告)号：US20080002335A1
公开(公告)日：2008-01-03
申请号：US11662368
申请日：2005-10-11
申请人： Junichi Kurita , Tsuyoshi Yoshino , Hirotoshi Toji , Kazuo Kawahito , Takashi Iwakiri , Hiroshi Serikawa , Kenji Kuranuki
发明人： Junichi Kurita , Tsuyoshi Yoshino , Hirotoshi Toji , Kazuo Kawahito , Takashi Iwakiri , Hiroshi Serikawa , Kenji Kuranuki
CPC分类号： H01G9/012 , H01G9/15 , Y10T29/41 , Y10T29/417
摘要： A solid electrolytic capacitor includes a planar solid electrolytic capacitor element having anode and cathode portions; anode and cathode terminals; and insulating coating resin. The anode terminal is electrically connected at the top surface thereof to the anode portion. The cathode terminal is electrically connected at the top surface side thereof to the cathode portion. The coating resin integrally coats the capacitor element so as to expose the bottom surfaces of the anode and cathode terminals. The anode and cathode terminals are disposed as close to each other as not more than 3 mm. The anode and cathode terminals have stair steps on both sides thereof and are connected to the anode and cathode portions at joint faces, respectively. The anode joint faces and the cathode joint faces are coated with coating resin. The solid electrolytic capacitor is provided with the anode joint faces and/or the cathode joint faces.
摘要翻译： 固体电解电容器包括具有阳极和阴极部分的平面固体电解电容器元件; 阳极和阴极端子; 和绝缘涂料树脂。 阳极端子在其顶表面处电连接到阳极部分。 阴极端子在其顶表面侧电连接到阴极部分。 涂覆树脂整体地涂覆电容器元件以暴露阳极和阴极端子的底表面。 阳极和阴极端子彼此靠近设置为不大于3mm。 阳极和阴极端子在其两侧具有阶梯台阶，并且分别在接合面处连接到阳极和阴极部分。 阳极接合面和阴极接合面用涂布树脂涂覆。 固体电解电容器设置有阳极接合面和/或阴极接合面。
-
5.发明授权Solid-electrolyte capacitor, manufacturing method thereof, and digital signal processing substrate using the solid-electrolyte capacitor 有权固体电解质电容器及其制造方法以及使用固体电解质电容器的数字信号处理基板公开(公告)号：US07365961B2
公开(公告)日：2008-04-29
申请号：US11662368
申请日：2005-10-11
申请人： Junichi Kurita , Tsuyoshi Yoshino , Hirotoshi Toji , Kazuo Kawahito , Takashi Iwakiri , Hiroshi Serikawa , Kenji Kuranuki
发明人： Junichi Kurita , Tsuyoshi Yoshino , Hirotoshi Toji , Kazuo Kawahito , Takashi Iwakiri , Hiroshi Serikawa , Kenji Kuranuki
IPC分类号： H01G9/00
CPC分类号： H01G9/012 , H01G9/15 , Y10T29/41 , Y10T29/417
摘要： A solid electrolytic capacitor includes a planar solid electrolytic capacitor element having anode and cathode portions; anode and cathode terminals; and insulating coating resin. The anode terminal is electrically connected at the top surface thereof to the anode portion. The cathode terminal is electrically connected at the top surface side thereof to the cathode portion. The coating resin integrally coats the capacitor element so as to expose the bottom surfaces of the anode and cathode terminals. The anode and cathode terminals are disposed as close to each other as not more than 3 mm. The anode and cathode terminals have stair steps on both sides thereof and are connected to the anode and cathode portions at joint faces, respectively. The anode joint faces and the cathode joint faces are coated with coating resin. The solid electrolytic capacitor is provided with the anode joint faces and/or the cathode joint faces.
摘要翻译： 固体电解电容器包括具有阳极和阴极部分的平面固体电解电容器元件; 阳极和阴极端子; 和绝缘涂料树脂。 阳极端子在其顶表面处电连接到阳极部分。 阴极端子在其顶表面侧电连接到阴极部分。 涂覆树脂整体地涂覆电容器元件以暴露阳极和阴极端子的底表面。 阳极和阴极端子彼此靠近设置为不大于3mm。 阳极和阴极端子在其两侧具有阶梯台阶，并且分别在接合面处连接到阳极和阴极部分。 阳极接合面和阴极接合面用涂布树脂涂覆。 固体电解电容器设置有阳极接合面和/或阴极接合面。
-
公开(公告)号：US06236561B1
公开(公告)日：2001-05-22
申请号：US09334771
申请日：1999-06-16
IPC分类号： H01G900
CPC分类号： H01G9/012
摘要： A chip type solid electrolytic capacitor of the present invention has a section formed in a step-wise manner on a cathode lead frame that is connected with a capacitor element. An anode lead wire of the capacitor element is resistance welded to the top of a reversed V-letter shaped structure formed by folding part of an anode lead frame into halves. Further, with the chip type solid electrolytic capacitor of the present invention, part of respective cathode and anode lead frames is exposed outside in such a way as being made flush with the periphery of a resin package, thereby each serving as a terminal. Accordingly, a space problem due to the terminals has been eliminated and the anode lead wire can be made short, thus allowing the volume of a capacitor element employed to be increased. As a result, a chip type solid electrolytic capacitor having a large capacity with its outer dimensions is kept the same as a prior art capacitor can be obtained.
摘要翻译： 本发明的芯片式固体电解电容器具有在与电容器元件连接的阴极引线框上逐步形成的部分。 电容器元件的阳极引线被电阻焊接到通过将阳极引线框架的一部分折叠成半部而形成的反向V字形结构的顶部。 此外，对于本发明的芯片型固体电解电容器，将阴极和阳极引线框架的一部分暴露在外部，使其与树脂封装的周边齐平，从而各自用作端子。 因此，由于端子引起的空间问题已被消除，并且可以使阳极引线短，从而允许增加使用的电容器元件的体积。 结果，具有外形尺寸大的芯片型固体电解电容器保持与现有技术的电容器相同。
-
公开(公告)号：US5629225A
公开(公告)日：1997-05-13
申请号：US478635
申请日：1995-06-07
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/60 , H01L28/91
摘要： A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.
摘要翻译： 一种用于包含屏幕型结构的圆柱形堆叠单元电容器的动态RAM的制造方法。 SiO 2层22形成在多晶硅层11（或半导体衬底1）上，用作预成型件或间隔件。 氮化物层31层叠在该SiO 2层上，氮化物层31和SiO 2层22被加工成几乎相同的图案。 然后，使用氮化物层31作为掩模来蚀刻SiO 2层22的外表面，使得氮化物层31在通过蚀刻去除的区域中形成横向突起结构31A。 多晶硅层23从包括该突出部分的氮化物层31和SiO 2层22的顶部附着到用作电容器下电极的硅层11的顶部。 蚀刻多晶硅层23，以在氮化物层31的突出部分31A正下方的SiO 2层22的外表面上留下多晶硅层23的一部分。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.021 秒)
