公开(公告)号：US4850078A

公开(公告)日：1989-07-25

申请号：US260871

申请日：1988-10-21

申请人： Scott A. Libby ,  Frank V. Pliml, Jr. ,  William M. Johnson ,  Laurence P. Armstrong ,  James L. Peterson

发明人： Scott A. Libby ,  Frank V. Pliml, Jr. ,  William M. Johnson ,  Laurence P. Armstrong ,  James L. Peterson

IPC分类号： E05D15/06

CPC分类号： E05D15/0669 ,  E05Y2201/638 ,  E05Y2201/64 ,  E05Y2600/53 ,  E05Y2900/132 ,  Y10T16/3819 ,  Y10T16/3834

摘要： An adjustable roller assembly for sliding doors including a housing adapted to be snap-fit into a recess provided in the upper or lower surface of a door frame, the housing defining a cavity which is open at the lower end. A roller carrier is mounted in the housing cavity and is vertically adjustable with respect to the housing. The lower end of the roller carrier defines circular flanges in which is rotatably mounted a roller having an integral hub. A camming arrangement associated with the roller carrier is accessible for adjustment from the side of the door frame and is operable to adjust the vertical position of the roller carrier and roller to adjust the slack between the door and the track upon which the roller is adapted to ride.

摘要翻译： 一种用于滑动门的可调节辊组件，其包括适于卡扣配合到设置在门框的上表面或下表面中的凹部中的壳体，壳体限定在下端敞开的空腔。 辊架安装在壳体腔体中并且相对于壳体可垂直调节。 滚子载体的下端形成圆形凸缘，其中可旋转地安装有具有一体式毂的滚子。 与辊架相关联的凸轮布置可从门框的侧面进行调节，并且可操作以调节滚轮托架和滚子的垂直位置，以调整门与滚子适用于的轨道之间的松弛度 骑。

公开(公告)号：US08185262B2

公开(公告)日：2012-05-22

申请号：US12763427

申请日：2010-04-20

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： G06F7/00 ,  B64G1/36

CPC分类号： B64G1/361 ,  B64G1/281 ,  G01S3/7862 ,  G05D1/0883

摘要： A method of and apparatus for determining and controlling the inertial attitude of a spinning artificial satellite without using a suite of inertial gyroscopes. The method and apparatus operate by tracking three astronomical objects near the Earth's ecliptic pole and the satellite's and/or star tracker's spin axis and processing the track information. The method and apparatus include steps and means for selecting preferably three astronomical objects using a histogram method and determining a square of a first radius (R12) of a track of a first astronomical object; determining a square of a second radius (R22) of a track of a second astronomical object; determining a square of a third radius (R32) of a track of a third astronomical object; determining the inertial attitude of the spin axis using the squares of the first, second, and third radii (R12, R22, and R32) to calculate pitch, yaw, and roll rate; determining a change in the pitch and yaw of the artificial satellite; and controlling on-board generated current flow to various orthogonally-disposed current-carrying loops to act against the Earth's magnetic field and to apply gyroscopic precession to the spinning satellite to correct and maintain its optimum inertial attitude.

摘要翻译： 用于在不使用一套惯性陀螺仪的情况下确定和控制旋转人造卫星的惯性姿态的方法和装置。 该方法和装置通过跟踪地球黄道附近的三个天文物体和卫星和/或星形跟踪器的自旋轴进行操作并处理轨道信息。 所述方法和装置包括使用直方图方法优选地选择三个天文物体并且确定第一天文物体的轨道的第一半径（R12）的平方的步骤和装置; 确定第二天文物体的轨道的第二半径（R22）的平方; 确定第三天文物体的轨道的第三半径（R32）的平方; 使用第一，第二和第三半径（R12，R22和R32）的平方来确定旋转轴的惯性姿态来计算俯仰，偏航和滚动速率; 确定人造卫星的俯仰和偏航的变化; 并且控制板上产生的电流流向各种正交布置的载流回路，以对地球的磁场起作用，并对旋转卫星施加陀螺进动，以校正和保持其最佳惯性姿态。

公开(公告)号：US08000735B1

公开(公告)日：2011-08-16

申请号：US11001491

申请日：2004-12-01

申请人： Michael Barclay ,  Terry Lynn Cole ,  Richard Powell ,  William M. Johnson ,  David W. Smith ,  Ralf Findeisen ,  Derek Golightly

发明人： Michael Barclay ,  Terry Lynn Cole ,  Richard Powell ,  William M. Johnson ,  David W. Smith ,  Ralf Findeisen ,  Derek Golightly

IPC分类号： H04M1/00

CPC分类号： H04W88/02

摘要： A wireless communications device includes a host processing unit, a modem processing unit, and a memory transport interface. The wireless communications device typically runs a variety of software tasks, some of which require considerably more memory than others. By processing the memory intensive tasks with the host processing unit and assigning tasks requiring high computing power but relatively smaller memory to the modem processor unit, a smaller on-chip memory can be used for the modem processor unit tasks. In addition, by using a messaging transport interface to transfer data between tasks running on different processing units, smaller local memories can be used in place of a shared memory. For example, by allocating and storing L1 tasks at the modem processing unit and allocating/storing L2 and L3 tasks at the host processing unit, duplicate memory components may be reduced or removed, thereby lowering system costs and improving system efficiency.

摘要翻译： 无线通信设备包括主机处理单元，调制解调器处理单元和存储器传输接口。 无线通信设备通常运行各种软件任务，其中一些需要比其他任务更多的存储器。 通过使用主机处理单元处理存储器密集型任务并且为调制解调器处理器单元分配需要高计算能力但是相对较小的存储器的任务，可以使用较小的片上存储器用于调制解调器处理器单元任务。 此外，通过使用消息传送接口在不同处理单元之间运行的任务之间传送数据，可以使用较小的本地存储器代替共享存储器。 例如，通过在调制解调器处理单元分配和存储L1任务并在主处理单元分配/存储L2和L3任务，可以减少或移除重复的存储器组件，从而降低系统成本并提高系统效率。

公开(公告)号：US20090222153A1

公开(公告)日：2009-09-03

申请号：US12363959

申请日：2009-02-02

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： G05D1/00 ,  B64G1/36 ,  G01C21/24

CPC分类号： B64G1/281 ,  B64G1/32 ,  B64G1/361 ,  B64G1/363 ,  B64G1/365 ,  B64G1/44 ,  G01S3/7862 ,  G05D1/0883

摘要： A method of and apparatus for determining and controlling the inertial attitude of a spinning artificial satellite without using a suite of inertial gyroscopes. The method and apparatus operate by tracking three astronomical objects near the Earth's ecliptic pole and the satellite's and/or star tracker's spin axis and processing the track information. The method and apparatus include steps and means for selecting preferably three astronomical objects using a histogram method and determining a square of a first radius (R12) of a track of a first astronomical object; determining a square of a second radius (R22) of a track of a second astronomical object; determining a square of a third radius (R32) of a track of a third astronomical object; determining the inertial attitude of the spin axis using the squares of the first, second, and third radii (R12, R22, and R32) to calculate pitch, yaw, and roll rate; determining a change in the pitch and yaw of the artificial satellite; and controlling on-board generated current flow to various orthogonally-disposed current-carrying loops to act against the Earth's magnetic field and to apply gyroscopic precession to the spinning satellite to correct and maintain its optimum inertial attitude.

摘要翻译： 用于在不使用一套惯性陀螺仪的情况下确定和控制旋转人造卫星的惯性姿态的方法和装置。 该方法和装置通过跟踪地球黄道附近的三个天文物体和卫星和/或星形跟踪器的自旋轴进行操作并处理轨道信息。 所述方法和装置包括使用直方图方法优选地选择三个天文物体并且确定第一天文物体的轨道的第一半径（R12）的平方的步骤和装置; 确定第二天文物体的轨道的第二半径（R22）的平方; 确定第三天文物体的轨道的第三半径（R32）的平方; 使用第一，第二和第三半径（R12，R22和R32）的平方来确定旋转轴的惯性姿态来计算俯仰，偏航和滚动速率; 确定人造卫星的俯仰和偏航的变化; 并且控制板上产生的电流流向各种正交布置的载流回路，以对地球的磁场起作用，并对旋转卫星施加陀螺进动，以校正和保持其最佳惯性姿态。

公开(公告)号：US06279101B1

公开(公告)日：2001-08-21

申请号：US08474791

申请日：1995-06-07

申请人： David B. Witt ,  William M. Johnson

发明人： David B. Witt ,  William M. Johnson

IPC分类号： G06F938

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

摘要： A super-scalar microprocessor performs operations upon a plurality of instructions at each of its fetch, decode, execute, and write-back stages. To support such operations, the super-scalar microprocessor includes a dispatch arrangement including an instruction cache for fetching blocks of instructions including a plurality of instructions and an instruction decoder which decodes and dispatches the instructions to functional units for execution. The instruction decoder applies a dispatch criteria to selected instructions of each block of instructions and dispatches the selected instructions which satisfy the dispatch criteria. The dispatch criteria includes the requirement that the instructions be dispatched speculatively in order, that supporting operands be available for the execution of the instructions, or tagged values substituted that will be available later, and that the functional units required for executing the instructions be available. The operation of the instruction decoder and the instruction cache is coordinated by a preset protocol which assures that the instructions are dispatched in ascending consecutive order and that blocks of instructions are efficiently fetched for decode and dispatch by the instruction decoder.

摘要翻译： 超标量微处理器在其每个读取，解码，执行和回写阶段对多个指令执行操作。 为了支持这种操作，超标量微处理器包括调度装置，其包括用于获取包括多个指令的指令块的指令高速缓存器以及将指令解码并分派到功能单元以执行的指令解码器。 指令解码器将调度标准应用于每个指令块的选择指令，并且调度满足调度准则的选定指令。 调度标准包括要求按顺序推测指令，支持操作数可用于执行指令，或替换为稍后可用的标记值，以及执行指令所需的功能单元可用。 指令解码器和指令高速缓存的操作由预设协议协调，该协议确保以上升的顺序分派指令，并且指令块被有效地提取以由指令解码器进行解码和分派。

公开(公告)号：US06256728B1

公开(公告)日：2001-07-03

申请号：US09110519

申请日：1998-07-06

申请人： David B. Witt ,  William M. Johnson

发明人： David B. Witt ,  William M. Johnson

IPC分类号： G06F1500

CPC分类号： G06F12/0897 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/30069 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/3842 ,  G06F12/0862

摘要： A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch instruction is predicted taken, instead of canceling subsequent instructions and fetching the branch target address, the processor allows sequential fetching to continue and selectively cancels the sequential instructions which are not part of the predicted instruction sequence (i.e. the instructions between the predicted taken branch instruction and the target instruction identified by the forward branch target address). Instructions within the predicted instruction sequence which may already have been fetched prior to predicting the branch instruction taken may be retained within the pipeline of the processor, and yet subsequent instructions may be fetched.

摘要翻译： 处理器被配置为检测分支指令具有在分支指令的分支取出地址的预定范围内的前向分支目标地址。 如果预测了分支指令，则代替取消后续指令并取出分支目标地址，处理器允许连续提取继续并选择性地取消不是预测指令序列的一部分的顺序指令（即预测的采用指令之间的指令 分支指令和由转发目标地址识别的目标指令）。 在预测分支指令之前可能已经获取的预测指令序列内的指令可以保留在处理器的流水线内，并且可以获取随后的指令。

公开(公告)号：US5903910A

公开(公告)日：1999-05-11

申请号：US561073

申请日：1995-11-20

申请人： Thang M. Tran ,  Marty L. Pflum ,  David B. Witt ,  William M. Johnson

发明人： Thang M. Tran ,  Marty L. Pflum ,  David B. Witt ,  William M. Johnson

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/30167 ,  G06F12/0875 ,  G06F9/30163 ,  G06F9/3824 ,  G06F9/3867

摘要： A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer. A signal is asserted by the first cache to inform the second cache of the need to perform a victim line copyback. Requests from the execute stage of the instruction processing pipeline are stalled to allow the copyback to occur.

摘要翻译： 提供了包括一对高速缓存的微处理器。 一对缓存中的一个通过来自指令处理流水线的解码级的堆栈相对存储器访问进行访问。 该对高速缓存中的第二个由指令处理流水线的执行阶段的存储器访问访问。 当在一对高速缓存中的第一个中检测到未命中时，丢失的堆栈相对存储器访问被传送到指令处理流水线的执行阶段。 当堆栈相对存储器访问访问该对高速缓存中的第二个时，包含访问的高速缓存行被发送到该对高速缓存中的第一个用于存储。 一对缓存中的第一个在从一对缓存中的第二个数据传输数据时选择一个受害者行进行替换。 如果受害者行已被存储在第一个缓存中被修改，那么受害者行将被存储在一个副本缓冲区中。 一个信号由第一个缓存断言，通知第二个缓存是否需要执行受害线回拷。 来自指令处理流水线的执行阶段的请求被停止以允许发生回拷。

公开(公告)号：US5651125A

公开(公告)日：1997-07-22

申请号：US501243

申请日：1995-07-10

申请人： David B. Witt ,  William M. Johnson

发明人： David B. Witt ,  William M. Johnson

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F15/167

CPC分类号： G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30174 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.

摘要翻译： 提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。 整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。 指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。 指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。 指令以推测顺序从解码器发出，发出无序，完成无序。 指令从重新排序缓冲区中重新排序到寄存器文件。 微处理器的功能单元期望地容纳显示多个数据宽度的操作数。 通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。

公开(公告)号：US4803615A

公开(公告)日：1989-02-07

申请号：US059167

申请日：1987-06-08

申请人： William M. Johnson

发明人： William M. Johnson

IPC分类号： G06F15/16 ,  G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/264 ,  G06F9/268 ,  G06F9/28 ,  G06F9/3853

摘要： A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro-operations are executed in subsequent cycles as a required subprocessor becomes available. The entire microinstruction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microinstruction are executed. At that time, the next microinstruction is fetched into the latch.

摘要翻译： 包括多个子处理器的微程序并行处理器在微指令的控制下操作。 每个微指令都包含多个微操作，每个微操作需要一个或多个子处理器执行。 立即执行所需的子处理器的所有微操作。 由于缺乏辅助处理器的可用性，微指令内的任何剩余微操作都不会被执行。 这些剩余的微操作在随后的循环中执行，因为所需的子处理器变得可用。 整个微指令不再循环，但只有那些部分，即未执行的微操作，在随后的循环中被回收和执行。 正在执行的微指令被存储在锁存器中，直到执行微指令内的所有微操作。 那时候，下一个微指令被取入锁存器。

公开(公告)号：US4788683A

公开(公告)日：1988-11-29

申请号：US143308

申请日：1988-01-07

申请人： Phillip D. Hester ,  William M. Johnson

发明人： Phillip D. Hester ,  William M. Johnson

IPC分类号： G01R31/3185 ,  G06F11/26 ,  G06F11/273 ,  G06F11/30

CPC分类号： G06F11/261 ,  G01R31/318505 ,  G01R31/318572 ,  G06F11/2733

摘要： Apparatus is provided for testing a data processing system which includes a microprocessor, the testing occurring with the microprocessor in place in the system. The apparatus comprises: a support microprocessor for controlling the testing, a serial-to-parallel and parallel-to-serial converter connected between the support microprocessor and the system microprocessor, means for supplying a series of level sensitive scan design (LSSD) test signals from the support microprocessor through the converter to the system microprocessor, and means for returning the results of the level sensitive scan design test signals from the system microprocessor through the converter to the support microprocessor.

摘要翻译： 提供了用于测试包括微处理器的数据处理系统的装置，该微处理器在系统中就位的测试发生。 该装置包括：用于控制测试的支持微处理器，连接在支持微处理器和系统微处理器之间的串并行和并 - 串转换器，用于提供一系列电平敏感扫描设计（LSSD）测试信号的装置 从支持微处理器通过转换器到系统微处理器，以及用于将来自系统微处理器的电平敏感扫描设计测试信号的结果通过转换器返回到支持微处理器的装置。