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公开(公告)号：US07259586B2
公开(公告)日：2007-08-21
申请号：US11115561
申请日：2005-04-27
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/1735 , H03K19/17732 , H03K19/17788 , H03K19/17796
摘要： An apparatus comprising an integrated circuit and a logic portion. The integrated circuit may have a plurality of regions each (i) pre-diffused and configured to be metal-programmed and (ii) configured to connect the integrated circuit to a socket. The logic portion may be implemented on the integrated circuit. The plurality of metal programmable regions are each (i) independently programmable and (ii) located in one of said pre-diffused regions. Each of the metal programmable regions comprises (a) a regulator section configured to generate an operating voltage from a common supply voltage, (b) a logic section configured to implement integrated circuit functions and operate at the operating voltage, and (c) a level shifter configured to shift the operating voltage to an external voltage level.
摘要翻译： 一种包括集成电路和逻辑部分的装置。 集成电路可以具有多个区域，每个区域（i）预扩散并被配置为金属编程，并且（ii）被配置为将集成电路连接到插座。 逻辑部分可以在集成电路上实现。 多个金属可编程区域各自（i）可独立编程，并且（ii）位于所述预扩散区域之一中。 每个金属可编程区域包括：（a）调节器部分，被配置为从公共电源电压产生工作电压，（b）逻辑部分，被配置为实现集成电路功能并在工作电压下工作，以及（c） 移位器被配置为将工作电压转换到外部电压电平。
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2.发明授权Use of configurable mixed-signal building block functions to accomplish custom functions 有权使用可配置的混合信号构建块功能来完成自定义功能公开(公告)号：US07478354B2
公开(公告)日：2009-01-13
申请号：US11133815
申请日：2005-05-20
IPC分类号： G06F17/50
CPC分类号： H01L27/118 , G06F17/5068 , H01L27/0207 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.
摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括在第一制造阶段期间仅制造直到并包括第一金属层的芯片，使得芯片的输入/输出（I / O）区域具有多个槽，其中， 槽具有多个第一晶体管。 该方法的第二步可以包括响应于在第一制造开始之后创建的定制设计来设计在第一金属层上方的多个上金属层，上金属层将多个第一晶体管互连以形成多个 混合信号构建块功能。 该方法的第三步可以涉及制造芯片以在第二制造阶段添加上金属层。
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公开(公告)号：US07360178B2
公开(公告)日：2008-04-15
申请号：US11136180
申请日：2005-05-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may include fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step generally involves designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form (i) a mixed-signal module and (ii) a digital module, the mixed signal module generating at least one analog signal and at least one digital signal. In a third step, the method may include fabricating the chip to add the upper metal layers.
摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括仅制造直到并包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 第二步通常包括响应于在第一制造开始之后产生的定制设计而在第一金属层之上设计多个上金属层，上金属层互连多个单元以形成（i）混合信号 模块和（ii）数字模块，所述混合信号模块产生至少一个模拟信号和至少一个数字信号。 在第三步骤中，该方法可以包括制造芯片以添加上部金属层。
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4.发明授权Relocatable built-in self test (BIST) elements for relocatable mixed-signal elements 有权可重定位的内置自检（BIST）元素，用于可重定位的混合信号元素公开(公告)号：US07373622B2
公开(公告)日：2008-05-13
申请号：US11129547
申请日：2005-05-13
IPC分类号： G06F17/50
CPC分类号： G01R31/31704 , G01R31/3167
摘要： An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.
摘要翻译： 一种包括平台专用集成电路（ASIC）的基础层，混合信号功能和内置自检（BIST）功能的装置。 平台ASIC的基础层通常包括围绕平台ASIC的外围设置的多个预扩散区域。 每个预扩散区域通常被配置为金属可编程的。 混合信号功能可以包括由设置在多个预扩散区域的第一数量上的金属掩模组形成的两个或更多个子功能。 BIST功能可以形成有放置在多个预扩散区域的第二数量上的金属掩模组。 BIST功能可以被配置为测试混合信号功能并呈现指示混合信号功能的操作条件的数字信号。
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公开(公告)号：US07305646B2
公开(公告)日：2007-12-04
申请号：US11125307
申请日：2005-05-09
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5045
摘要： An apparatus that may include a base layer of a platform application specific integrated circuit (ASIC) and a mixed-signal function. The base layer of the platform application specific integrated circuit (ASIC) generally comprises a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions may be configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a number of the plurality of pre-diffused regions.
摘要翻译： 可以包括平台专用集成电路（ASIC）的基础层和混合信号功能的装置。 平台应用专用集成电路（ASIC）的基层通常包括围绕平台ASIC的外围设置的多个预扩散区域。 每个预扩散区域可以被配置为金属可编程的。 混合信号功能可以包括由置于多个预扩散区域的多个上的金属掩模组形成的两个或更多个子功能。
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公开(公告)号：US07373629B2
公开(公告)日：2008-05-13
申请号：US11113615
申请日：2005-04-25
CPC分类号： H01L27/11898 , H01L27/0207
摘要： An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.
摘要翻译： 一种包括集成电路的装置，其具有（i）多个区域，每个区域预扩散并被配置为金属编程;以及（ii）多个引脚，被配置为将集成电路连接到插座。 逻辑部分可以在被配置为实现集成电路操作的集成电路（i）上实现，并且（ii）具有一个或多个I / O连接和一个或多个供电连接。 预扩散区域的第一组被金属编程并耦合到所述I / O连接。 第二组预扩散区域是金属编程的，并且耦合到电源连接。
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7.发明授权Method of interconnect for multi-slot metal-mask programmable relocatable function placed in an I/O region 失效用于多槽金属掩模可编程可重定位功能的互连方法放置在I / O区域中公开(公告)号：US07292063B2
公开(公告)日：2007-11-06
申请号：US11120067
申请日：2005-05-02
CPC分类号： H01L27/11898 , G06F17/5077 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： A method for interconnecting sub-functions of metal-mask programmable functions that includes the steps of (A) forming a base layer of a platform application specific integrated circuit (ASIC) comprising a plurality of pre-diffused regions disposed around a periphery of the platform ASIC, (B) forming two or more sub-functions of a function with a metal mask set placed over a number of the plurality of pre-diffused regions of the platform application specific integrated circuit and (C) configuring one or more connection points in each of the two or more sub-functions such that interconnections between the two or more sub-functions are tool routable in a single layer. Each of the pre-diffused regions is configured to be metal-programmable.
摘要翻译： 一种用于互连金属掩模可编程功能的子功能的方法，其包括以下步骤：（A）形成平台应用专用集成电路（ASIC）的基层，所述平台专用集成电路（ASIC）包括围绕所述平台周围设置的多个预扩散区域 ASIC，（B）形成功能的两个或更多个子功能，其中金属掩模集放置在平台应用专用集成电路的多个预扩散区域的数量上，以及（C）配置一个或多个连接点 两个或更多个子功能中的每一个，使得两个或多个子功能之间的互连是可在单个层中可路由的工具。 每个预扩散区域被配置为金属可编程的。
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公开(公告)号：US07272802B2
公开(公告)日：2007-09-18
申请号：US11126880
申请日：2005-05-11
申请人： Donald T. McGrath , Scott C. Savage
发明人： Donald T. McGrath , Scott C. Savage
IPC分类号： G06F17/50
CPC分类号： H01L27/0251 , H01L2924/0002 , H03K19/173 , H01L2924/00
摘要： A method for producing a chip is disclosed. A first step of the method may involve first fabricating the chip only up to and including a first metal layer such that a core region of the chip has an array of cells, each of the cells having a plurality of transistors. A second step of the method may be to design a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the cells to form an electrostatic discharge clamp at a power domain crossing. A third step may include second fabricating the chip to add the upper metal layers.
摘要翻译： 公开了一种芯片的制造方法。 该方法的第一步可以包括首先制造仅包括第一金属层并且包括第一金属层的芯片，使得芯片的芯区域具有单元阵列，每个单元具有多个晶体管。 该方法的第二步可以是响应于在第一制造开始之后产生的定制设计，在第一金属层上方设计多个上金属层，上金属层将多个单元互连以形成静电放电 夹在电源交叉口。 第三步骤可以包括第二制造芯片以添加上金属层。
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公开(公告)号：US07566923B2
公开(公告)日：2009-07-28
申请号：US11318332
申请日：2005-12-23
申请人： Donald T. McGrath , Gregory Winn , Scott C. Savage
发明人： Donald T. McGrath , Gregory Winn , Scott C. Savage
IPC分类号： H01L27/118
CPC分类号： H03K19/1736 , H01L27/0207 , H01L27/11807
摘要： A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.
摘要翻译： 一种包括基础层的平台专用集成电路（ASIC）。 基本层通常包括预定义的输入/输出（I / O）区域和预定义的核心区域。 预定义的输入/输出（I / O）区域可以包括布置在平台ASIC中的多个预扩散区域。 预定义的芯区域可以包括一个或多个限定根据在制造基层之后创建的定制设计形成的多个功率区域的金属层。 可以通过沉积一个或多个金属层来定制基层。
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公开(公告)号：US06242897B1
公开(公告)日：2001-06-05
申请号：US09497652
申请日：2000-02-03
申请人： Scott C. Savage , Ricky F. Bitting
发明人： Scott C. Savage , Ricky F. Bitting
IPC分类号： G05F316
CPC分类号： G05F3/30
摘要： An on-chip voltage reference supply operates in the current domain rather than the voltage domain, implemented with a single diode drop to reduce power supply headroom requirements. A plurality of current generators generate currents representing a first design voltage. A gain circuit responds to the currents to supply a gain voltage representing the sum of the first design voltages. A summing circuit sums the gain voltage and a second design voltage to derive the predetermined reference voltage.
摘要翻译： 片上电压参考电源在电流域中运行，而不是电压域，采用单个二极管降压实现，以减少电源余量要求。 多个电流发生器产生表示第一设计电压的电流。 增益电路响应电流以提供表示第一设计电压之和的增益电压。 求和电路将增益电压和第二设计电压相加以导出预定的参考电压。
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