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    Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
    5.
    发明授权
    Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers 失效
    使用多个填充缓冲器以非阻塞方式高速缓存数据的方法和装置

    公开(公告)号：US5671444A

    公开(公告)日：1997-09-23

    申请号：US731545

    申请日：1996-10-15

    申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0859 ,  G06F12/0831

    摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

    摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

    Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
    7.
    发明授权
    Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers 失效
    具有数据和标签数组的高速缓冲存储器系统以及具有多个行缓冲器的多用途缓冲器组件

    公开(公告)号：US5680572A

    公开(公告)日：1997-10-21

    申请号：US680109

    申请日：1996-07-15

    申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0859

    摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

    摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

    Apparatus and method for maintaining processing consistency in a computer system having multiple processors
    8.
    发明授权
    Apparatus and method for maintaining processing consistency in a computer system having multiple processors 失效
    用于在具有多个处理器的计算机系统中维持处理一致性的装置和方法

    公开(公告)号：US5420991A

    公开(公告)日：1995-05-30

    申请号：US177239

    申请日：1994-01-04

    申请人： Kris G. Konigsfeld ,  Jeffrey M. Abramson ,  Haitham Akkary ,  Glenn J. Hinton ,  Andrew F. Glew

    发明人： Kris G. Konigsfeld ,  Jeffrey M. Abramson ,  Haitham Akkary ,  Glenn J. Hinton ,  Andrew F. Glew

    IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F9/46

    CPC分类号： G06F9/30043 ,  G06F12/0831 ,  G06F9/3834

    摘要： An apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively. Speculative loads of each processor are temporarily stored in their respective processors' load buffer. When one of the processors performs a store, a snoop operation is performed on the other processors' load buffers. If the snoop results in a hit, a determination is made as to whether that load buffer contains any prior conflicting speculative loads which have been completed. If the load buffer does contain a prior conflicting load, a processor ordering violation signal is generated. In response to this signal, the violating load and all subsequent operations are canceled and re-executed at a later time.

    摘要翻译： 一种用于在多处理器计算机系统中维持处理器排序的装置，其中负载被推测地执行。 每个处理器的推测负载临时存储在它们各自的处理器的负载缓冲器中。 当其中一个处理器执行存储时，对其他处理器的负载缓冲区执行窥探操作。 如果窥探导致命中，则确定该加载缓冲器是否包含已经完成的任何先前冲突的推测负载。 如果加载缓冲区确实包含先前存在冲突的负载，则会生成处理器排序违规信号。 响应于该信号，违反负载和所有后续操作将在以后被取消并重新执行。

    Method and apparatus for calculating effective memory addresses
    9.
    发明授权
    Method and apparatus for calculating effective memory addresses 失效
    用于计算有效存储器地址的方法和装置

    公开(公告)号：US5860154A

    公开(公告)日：1999-01-12

    申请号：US778969

    申请日：1997-01-06

    申请人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mark A. Timko

    发明人： Jeffrey M. Abramson ,  Haitham Akkary ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mark A. Timko

    IPC分类号： G06F9/318 ,  G06F9/355 ,  G06F12/00

    CPC分类号： G06F9/3555 ,  G06F9/3017

    摘要： A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

    摘要翻译： 为微处理器提供宏指令，允许程序员指定基值，索引，比例因子和位移值，用于计算有效地址并在单个时钟周期内返回该结果。 宏指令被转换为微操作，其被提供给具有用于执行计算的所需源操作数的单周期执行单元。 在单周期执行单元内，将索引和比例因子提供给用于乘以两个值的左移位器。 左移操作的结果被加到底座和位移之和上。 这导致有效地址然后从单周期执行单元返回到预定的目的地。 这提供了独立于存储器系统执行单元的单周期流水线执行单元中的有效地址的计算。