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1.发明授权
公开(公告)号：US5636374A
公开(公告)日：1997-06-03
申请号：US470842
申请日：1995-06-06
申请人： Scott D. Rodgers , Keshavan K. Tiruvallur , Michael W. Rhodehamel , Kris G. Konigsfeld , Andrew F. Glew , Haitham Akkary , Milind A. Karnik , James A. Brayton
发明人： Scott D. Rodgers , Keshavan K. Tiruvallur , Michael W. Rhodehamel , Kris G. Konigsfeld , Andrew F. Glew , Haitham Akkary , Milind A. Karnik , James A. Brayton
CPC分类号： G06F9/30043 , G06F12/0891 , G06F12/1027
摘要： In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.
摘要翻译： 在微处理器中，用于执行存储器功能并发布总线周期的装置和方法。 特殊的微指令存储在微码ROM中。 这些微指令用于执行存储器功能并产生特殊的总线周期。 最初，对于这些特殊微指令之一产生与要执行的请求操作相对应的地址。 该特殊微指令及其地址然后通过总线传输到微处理器的各个单元。 当每个单元接收微指令时，它根据该地址确定该微指令是否被忽略。 如果特定单元忽略微指令，则微指令将转发到管道中的后续单元进行处理。 否则，如果该特定单元执行由微指令的地址指定的请求操作。
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公开(公告)号：US07769938B2
公开(公告)日：2010-08-03
申请号：US11850790
申请日：2007-09-06
申请人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
发明人： Shivnandan D. Kaushik , Keshavan K. Tiruvallur , James B. Crossland , Sridhar Muthrasanallur , Rajesh S. Parthasarathy , Luke P. Hood
CPC分类号： G06F9/505 , G06F9/3885 , G06F9/3891 , G06F9/5094 , G06F13/24 , Y02D10/14 , Y02D10/22
摘要： In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described.
摘要翻译： 在一些实施例中，一种装置包括处理器选择逻辑，以接收与每个具有处理器集群标识号的中断相关联的逻辑目的地标识号，以识别中断指向的处理器的集群。 逻辑目的地识别号码各自用于识别所识别的处理器簇内的哪些处理器可用于接收相应的一个中断。 处理器选择逻辑是选择一个可用的处理器来接收中断，并且通过逻辑目的地标识号中的对应位的相对位置来识别所选择的一个可用处理器。 描述其他实施例。
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公开(公告)号：US07596653B2
公开(公告)日：2009-09-29
申请号：US10984527
申请日：2004-11-08
CPC分类号： G06F13/36
摘要： A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.
摘要翻译： 一种通过点对点网络广播消息的技术。 更具体地，本发明的实施例涉及在点对点互连之间的电子部件之间广播消息。
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4.发明授权公开(公告)号：US06708269B1
公开(公告)日：2004-03-16
申请号：US09475098
申请日：1999-12-30
申请人： Keshavan K. Tiruvallur , Douglas M. Carmean , Robert J. Greiner , Muntaquim Chowdhury , Madhavan Parthasarathy
发明人： Keshavan K. Tiruvallur , Douglas M. Carmean , Robert J. Greiner , Muntaquim Chowdhury , Madhavan Parthasarathy
IPC分类号： G06F9312
CPC分类号： G06F9/3824 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3842 , G06F9/3851
摘要： In a multi-threaded system, such as in a multi-processor system, different types of fences are provided to force completion of programmatically earlier instructions in a program. The types of fences can be thread-specific, and different types of fences are used based on different kinds of conditions, instructions, operations, or memory types. When a fence is executed, senior stores, request buffers, bus queues, or any combination of these stages in an execution pipeline can be drained. Fetches at a front end of the pipeline can also be killed to ensure that the bus queue can be drained.
摘要翻译： 在多线程系统中，例如在多处理器系统中，提供了不同类型的围栏，以强制程序化程序中早期指令的完成。 栅栏的类型可以是线程特定的，并且基于不同种类的条件，指令，操作或存储器类型使用不同类型的栅栏。 执行栅栏时，执行管道中的高级存储，请求缓冲区，总线队列或这些阶段的任意组合可能会被排除。 管道前端的汲取也可能被杀死，以确保总线队列可以排空。
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公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译： 这里描述了一种用于提供测试，验证和调试架构的装置和方法。 在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。 控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。 此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。 此外，该架构可能提供对测试架构的分层（多级）安全访问。 此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。 本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。
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公开(公告)号：US08347018B2
公开(公告)日：2013-01-01
申请号：US12569772
申请日：2009-09-29
CPC分类号： G06F13/36
摘要： Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed.
摘要翻译： 描述了通过点对点网络广播消息的技术。 更具体地，本发明的一些实施例涉及在点对点互连之间的电子部件之间广播消息。 还公开了其他实施例。
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7.发明申请公开(公告)号：US20090070510A1
公开(公告)日：2009-03-12
申请号：US11966356
申请日：2007-12-28
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
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8.发明授权Processor selection for an interrupt based on willingness to accept the interrupt and on priority 有权处理器根据意愿接受中断和优先级中断进行选择公开(公告)号：US08032681B2
公开(公告)日：2011-10-04
申请号：US11966356
申请日：2007-12-28
CPC分类号： G06F13/24
摘要： In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described.
摘要翻译： 在一些实施例中，装置包括处理器，信号存储电路和处理器选择逻辑。 信号存储电路将保持意愿指示信号，每个指示相关联的一个处理器的意愿水平接收中断并保持指示相关联的一个处理器的处理器优先级的优先级指示信号，其中， 是多个可能的意愿水平和多个可能的处理器优先级。 处理器选择逻辑是至少基于意愿指示信号选择一个处理器来接收中断。 描述其他实施例。
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公开(公告)号：US10198333B2
公开(公告)日：2019-02-05
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
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10.发明授权Methods and tools to debug complex multi-core, multi-socket QPI based system 有权复杂多核，多插座QPI系统的调试方法与工具公开(公告)号：US08782468B2
公开(公告)日：2014-07-15
申请号：US13333952
申请日：2011-12-21
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： Methods and apparatus relating to debugging complex multi-core and/or multi-socket systems are described. In one embodiment, a debug controller detects an event corresponding to a failure in a computing system and transmits data corresponding to the event to one of the other debug controllers in the system. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与调试复杂多核和/或多插槽系统有关的方法和设备。 在一个实施例中，调试控制器检测与计算系统中的故障相对应的事件，并将与事件相对应的数据发送到系统中的其他调试控制器之一。 还公开并要求保护其他实施例。
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