公开(公告)号：US5687381A

公开(公告)日：1997-11-11

申请号：US599603

申请日：1996-02-09

申请人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

发明人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes a periodic interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one, and the microprocessor effectively prefetches the interrupt service routine before the interrupt is actually signaled. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur at the expiration of a programmable time interval. Another embodiment of the interrupt polling unit causes an interrupt acknowledge bus transaction subsequent to the occurrence of a bus transaction programmed by the user.

摘要翻译： 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致周期性中断确认总线事务发生。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个，并且微处理器在实际发出中断之前有效地预取中断服务程序。 在一个实施例中，中断轮询单元导致在可编程时间间隔期满时发生中断确认总线事务。 中断轮询单元的另一实施例在由用户编程的总线事务发生之后导致中断确认总线事务。

公开(公告)号：US5948093A

公开(公告)日：1999-09-07

申请号：US599618

申请日：1996-02-09

申请人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

发明人： Scott E. Swanstrom ,  David S. Christie ,  Steven L. Belt

IPC分类号： G06F9/32 ,  G06F9/48 ,  G06F9/22

CPC分类号： G06F9/4812 ,  G06F9/32

摘要： An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur when the microprocessor is performing a task switch. The task switch may be performed by hardware included within the microprocessor or, alternatively, by software executing upon the microprocessor.

摘要翻译： 提供了包括在微处理器的总线接口单元内的中断轮询单元。 中断轮询单元导致发生中断确认总线事务。 如果接收到中断确认总线事务的中断控制器返回指示中断服务程序的中断向量，则微处理器执行中断服务程序。 与中断相关联的中断确认总线事务数量从两个减少到一个。 在一个实施例中，当微处理器执行任务切换时，中断轮询单元导致中断确认总线事务发生。 任务切换可以由包括在微处理器内的硬件执行，或者由软件在微处理器上执行。

公开(公告)号：US08352688B2

公开(公告)日：2013-01-08

申请号：US12946743

申请日：2010-11-15

申请人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

发明人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack ,  Luke Yen

IPC分类号： G06F12/00

CPC分类号： G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

摘要： A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

公开(公告)号：US20120124563A1

公开(公告)日：2012-05-17

申请号：US12947336

申请日：2010-11-16

申请人： Jaewoong Chung ,  Rahmet Ulya Karpuzcu ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack

发明人： Jaewoong Chung ,  Rahmet Ulya Karpuzcu ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin T. Pohlack

IPC分类号： G06F9/45

CPC分类号： G06F8/447 ,  G06F9/467

摘要： A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.

摘要翻译： 提供了一种用于编译写入要在支持至少一个硬件事务存储器功能的微处理器上执行的软件的方法和装置。 支持至少一个软件事务性存储器功能的编译器适于包括在所述至少一个软件事务存储器功能与所述至少一个硬件事务存储器指令之间映射的运行时系统。

公开(公告)号：US20110040906A1

公开(公告)日：2011-02-17

申请号：US12627956

申请日：2009-11-30

申请人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack

发明人： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack

IPC分类号： G06F5/14 ,  G06F12/00

CPC分类号： G06F5/16 ,  G06F9/528

摘要： An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.

摘要翻译： 一种用于实现具有多级事务缓冲器的硬件事务存储器（HTM）系统的装置，方法和系统。 该装置包括数据高速缓存，其被配置为缓冲由推测性存储器访问操作访问的共享（多个处理核心）存储器中的数据，并且在至少一部分尝试期间保留数据以执行原子存储器事务。 该装置还包括：溢出检测电路，其被配置为在确定数据高速缓冲存储器不足以缓冲作为原子存储器事务的一部分访问的数据的一部分时检测溢出状况，以及配置为响应于检测的缓冲电路 通过防止数据部分被缓冲在数据高速缓冲存储器中并缓冲与数据高速缓存分开的辅助缓冲器中的数据的部分，来实现溢出状态。

公开(公告)号：US20080245529A1

公开(公告)日：2008-10-09

申请号：US11696814

申请日：2007-04-05

申请人： David S. Christie ,  Robert Voss ,  Peter Breese

发明人： David S. Christie ,  Robert Voss ,  Peter Breese

IPC分类号： E21B33/035

CPC分类号： E21B33/038 ,  E21B33/035

摘要： A subsea well assembly has a tubing hanger that lands and seals in a wellhead housing. A tree block is lowered through the drilling riser into engagement with the tubing hanger. The tree block has a lower portion that inserts and latches into the bore of the wellhead housing. The drilling riser is disconnected, and a module is lowered onto the tree block, the module having a choke and controls for controlling the well. The master valve for production is the downhole safety valve in the tubing. The wing production valve is a ball valve located in the flow passage of the tree block.

摘要翻译： 海底井组件具有在井口壳体中降落和密封的管道悬挂器。 一个树木块通过钻井提升器下降，与管道吊架接合。 树块具有将井口插入并锁定到井口壳体的孔中的下部。 钻井立管断开，模块下降到树块上，模块具有扼流圈和控制以控制井。 生产主阀是管道中的井下安全阀。 机翼生产阀是位于树块流道中的球阀。

公开(公告)号：US06981132B2

公开(公告)日：2005-12-27

申请号：US09825183

申请日：2001-04-02

申请人： David S. Christie ,  Kevin J. McGrath

发明人： David S. Christie ,  Kevin J. McGrath

IPC分类号： G06F9/30 ,  G06F9/318

CPC分类号： G06F9/3013 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/342 ,  G06F9/384

摘要： A processor changes the mapping of register addresses to registers dependent on an instruction field. In one particular embodiment, the mapping may be changed for byte addressing of the registers. A register mapping in which each register address maps to either the least significant byte or the next least significant byte of a subset of the registers may be supported, as well as a register mapping in which each register address maps to the least significant byte of each register, in one implementation. In one particular implementation, the instruction field may be a prefix field (e.g. a prefix byte). The processor may provide for uniform addressing of registers (e.g. byte addressing of the registers) responsive to a prefix field, in other embodiments, irrespective of the addressing provided if the prefix field is not included, or is encoded differently than the encoding which results in the uniform addressing.

摘要翻译： 处理器根据指令字段改变寄存器地址到寄存器的映射。 在一个特定实施例中，可以改变寄存器的字节寻址的映射。 每个寄存器地址映射到寄存器子集的最低有效字节或下一个最低有效字节的寄存器映射，以及寄存器映射，其中每个寄存器地址映射到每个寄存器地址的最低有效字节 在一个实现中注册。 在一个特定实现中，指令字段可以是前缀字段（例如前缀字节）。 响应于前缀字段，处理器可以提供对前缀字段的寄存器的均匀寻址（例如寄存器的字节寻址），而在其他实施例中，无论如果前缀字段不包括提供的寻址，或者编码的方式不同于导致 统一寻址。

公开(公告)号：US06810476B2

公开(公告)日：2004-10-26

申请号：US09824862

申请日：2001-04-02

申请人： Kevin J. McGrath ,  David S. Christie

发明人： Kevin J. McGrath ,  David S. Christie

IPC分类号： G06F9312

CPC分类号： G06F9/30043 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/342

摘要： A processor supports at least two different state save formats. Each format stores state in the form that the state exists in one or more operating modes of the processor. The operand size of the state save and state restore instructions may be used to indicate which state format is assumed by the processor during execution of the state save and state restore instructions. In one implementation, the processor implements a processor architecture compatible with the x86 architecture with enhancements to support 64 bit addressing and processing. In modes in which 64 bit addressing is supported, segmentation is not used. In 32 bit and 16 bit modes, segmentation is used. Thus, the address of a floating point instruction and/or operand may be indicated by a segment selector or pointer or by a pointer only.

公开(公告)号：US06757771B2

公开(公告)日：2004-06-29

申请号：US09920459

申请日：2001-08-01

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F900

CPC分类号： G06F9/342 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30189

摘要： A method and mechanism for performing an unconditional stack switch in a processor. A processor includes a processing unit coupled to a memory. The memory includes a plurality of stacks, a special mode task state segment, and a descriptor table. The processor detects interrupts and accesses a descriptor corresponding to the interrupt within the descriptor table. Subsequent to accessing the descriptor, the processor is configured to access an index within the descriptor in order to determine whether or not an interrupt stack table mechanism is enabled. In response to detecting the interrupt stack table mechanism is enabled, the index is used to select an entry in the interrupt stack table. The selected entry in the interrupt stack table indicates a stack pointer which is then used to perform an unconditional stack switch.

摘要翻译： 一种用于在处理器中执行无条件堆叠交换的方法和机制。 处理器包括耦合到存储器的处理单元。 存储器包括多个堆栈，特殊模式任务状态段和描述符表。 处理器检测中断并访问与描述符表中的中断相对应的描述符。 在访问描述符之后，处理器被配置为访问描述符内的索引，以便确定中断堆栈表机制是否被启用。 响应检测到中断堆栈表机制被使能，该索引用于在中断堆栈表中选择一个条目。 中断堆栈表中的选定项表示堆栈指针，然后用于执行无条件堆栈交换。

公开(公告)号：US06516395B1

公开(公告)日：2003-02-04

申请号：US09626615

申请日：2000-07-27

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F1214

CPC分类号： G06F12/1491

摘要： A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are allocated to access regions within a MSR file. Each access region of the MSR file is assigned access attributes. The MSRs are allocated such that the access region and the access attributes of the MSRs are defined by the address of the MSRs. Access to the MSRs is controlled by comparing the address of the MSR to the current privilege level of the microprocessor. In one embodiment, a validity check circuit is used to control access to the MSRs. If an access is attempted to an MSR that cannot be accessed at the current microprocessor privilege level, access to the register is denied and an exception is generated. In one embodiment, an address checker may be used to verify whether an MSR address is within a valid range. The MSR file may be divided into regions, with access granted based on a microprocessor being in a supervisory mode or a user mode.

摘要翻译： 用于控制对特定于模型的寄存器文件的特权分割地址空间的访问的系统和方法。 超标量微处理器包括多个型号特定寄存器（MSR）。 微处理器架构的各种实现之间的MSR不同。 MSR分配给MSR文件中的访问区域。 MSR文件的每个访问区域都被分配访问属性。 分配MSR使得MSR的接入区域和接入属性由MSR的地址定义。 通过将MSR的地址与微处理器的当前特权级别进行比较来控制对MSR的访问。 在一个实施例中，使用有效性检查电路来控制对MSR的访问。 如果尝试对当前微处理器权限级别无法访问的MSR进行访问，则拒绝对寄存器的访问，并生成异常。 在一个实施例中，可以使用地址检查器来验证MSR地址是否在有效范围内。 MSR文件可以被划分为区域，其中基于处于监控模式或用户模式的微处理器被准许访问。