公开(公告)号：US20060175297A1

公开(公告)日：2006-08-10

申请号：US11344049

申请日：2006-02-01

申请人： Se-rah Yun ,  Jeong-heon Park ,  Chang-ki Hong ,  Jae-dong Lee

发明人： Se-rah Yun ,  Jeong-heon Park ,  Chang-ki Hong ,  Jae-dong Lee

IPC分类号： H01L21/461 ,  B08B6/00 ,  B44C1/22 ,  C03C25/68

CPC分类号： H01L21/02074 ,  C11D1/146 ,  C11D3/2079 ,  C11D3/2082 ,  C11D3/2086 ,  C11D3/3409 ,  C11D11/0047

摘要： A metallization method for a semiconductor device, and a cleaning solution for the same, for cleaning a surface of a semiconductor substrate on which a metal wiring material is exposed. The metallization method may include cleaning a surface of a semiconductor substrate on which a metal wiring layer is exposed using a cleaning solution that includes deionized water, an organic acid, and at least one of an anionic surfactant and an amphoteric surfactant, and, after the cleaning, ashing the surface of the metal wiring layer.

摘要翻译： 一种用于半导体器件的金属化方法及其用于清洁其上露出金属布线材料的半导体衬底的表面的清洁溶液。 金属化方法可以包括使用包括去离子水，有机酸和阴离子表面活性剂和两性表面活性剂中的至少一种的清洗溶液来清洁其上暴露金属布线层的半导体基板的表面，以及在 清洁，灰化金属布线层的表面。

公开(公告)号：US07498263B2

公开(公告)日：2009-03-03

申请号：US11298678

申请日：2005-12-12

申请人： Se-rah Yun ,  Chang-ki Hong ,  Jae-dong Lee

发明人： Se-rah Yun ,  Chang-ki Hong ,  Jae-dong Lee

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31058 ,  H01L21/31053 ,  H01L21/76819

摘要： A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer.

摘要翻译： 提供一种形成平坦化的金属间绝缘膜的方法。 该方法包括将CMP工艺施加到由形成在下面的金属布线图案上的抛光 - 停止层图案控制的绝缘膜上。 可以使用基于PAE的材料来形成抛光 - 停止层。

公开(公告)号：US20060148258A1

公开(公告)日：2006-07-06

申请号：US11298678

申请日：2005-12-12

申请人： Se-rah Yun ,  Chang-ki Hong ,  Jae-dong Lee

发明人： Se-rah Yun ,  Chang-ki Hong ,  Jae-dong Lee

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31058 ,  H01L21/31053 ,  H01L21/76819

摘要： A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer.

公开(公告)号：US20090121296A1

公开(公告)日：2009-05-14

申请号：US12291211

申请日：2008-11-07

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L27/10

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US20120028435A1

公开(公告)日：2012-02-02

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US09035396B2

公开(公告)日：2015-05-19

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L27/14 ,  H01L29/76 ,  H01L21/3105 ,  H01L27/105 ,  H01L29/66

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

公开(公告)号：US08053845B2

公开(公告)日：2011-11-08

申请号：US12291211

申请日：2008-11-07

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/70

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。