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Patent Agency Ranking
公开(公告)号：US09548128B2
公开(公告)日：2017-01-17
申请号：US14961865
申请日：2015-12-07
Applicant: Seagate Technology LLC
IPC: H03M13/03 , G11C16/28 , H03M13/11 , G11C11/56 , G11C29/02 , G11C16/08 , G11C16/26 , G11C29/42 , G11C29/44
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C29/026 , G11C29/028 , G11C29/42 , G11C2029/4402 , H03M13/1117 , H03M13/1125
Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
Abstract translation: 用于读取非易失性存储器的装置包括跟踪模块，其可操作以计算非易失性存储器中的电压电平分布的平均值和方差，并且计算当基于所述非易失性存储器读取非易失性存储器时要使用的至少一个参考电压 平均值和方差，似然发生器可操作以计算在读取非易失性存储器时要使用的至少一个其它参考电压，其中至少一个其它参考电压至少部分地基于预定似然值星座，并且 将从非易失性存储器读取图案映射到似然值，以及读取控制器，其可操作以使用所述至少一个参考电压和所述至少一个其它参考电压来读取所述非易失性存储器以产生所述读取模式。
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公开(公告)号：US09459956B2
公开(公告)日：2016-10-04
申请号：US13958162
申请日：2013-08-02
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Alexander Hubris , Zhengang Chen , AbdelHakim S. Alhussien , YingQuan Wu
CPC classification number: G06F11/1048 , G06F11/10 , H03M13/1102 , H03M13/1105 , H03M13/1137 , H03M13/114 , H03M13/1142 , H03M13/116 , H03M13/1171 , H03M13/6561 , H03M13/658
Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.
Abstract translation: 低密度奇偶校验解码器包括可变节点处理器，其可操作以生成可变节点以校验节点消息，并且基于对可变节点消息的校验节点来计算感知值;校验节点处理器，可操作以将校验节点生成到可变节点消息向量;以及 基于变量节点来计算校验和以检查节点消息;以及收敛检测器和位图生成器，其可操作用于感知值的收敛并生成至少一个位图，其识别连接到具有不满足奇偶校验检查的节点的变量节点 。
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公开(公告)号：US20160093396A1
公开(公告)日：2016-03-31
申请号：US14961865
申请日：2015-12-07
Applicant: Seagate Technology LLC
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C29/026 , G11C29/028 , G11C29/42 , G11C2029/4402 , H03M13/1117 , H03M13/1125
Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
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公开(公告)号：US09209835B2
公开(公告)日：2015-12-08
申请号：US14135837
申请日：2013-12-20
Applicant: Seagate Technology LLC
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C29/026 , G11C29/028 , G11C29/42 , G11C2029/4402 , H03M13/1117 , H03M13/1125
Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
Abstract translation: 用于读取非易失性存储器的装置包括跟踪模块，其可操作以计算非易失性存储器中的电压电平分布的平均值和方差，并且计算当基于所述非易失性存储器读取非易失性存储器时要使用的至少一个参考电压 平均值和方差，似然发生器可操作以计算在读取非易失性存储器时要使用的至少一个其它参考电压，其中至少一个其它参考电压至少部分地基于预定似然值星座，并且 将从非易失性存储器读取图案映射到似然值，以及读取控制器，其可操作以使用所述至少一个参考电压和所述至少一个其它参考电压来读取所述非易失性存储器以产生所述读取模式。
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公开(公告)号：US09160367B2
公开(公告)日：2015-10-13
申请号：US14567607
申请日：2014-12-11
Applicant: Seagate Technology LLC
Inventor： YingQuan Wu
CPC classification number: H03M13/1128 , H03M13/1102 , H03M13/1117 , H03M13/13 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2942
Abstract: Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically encoding the at least second data element and the at least first truncated data element using the sparse parity check matrix H1 to obtain a nested codeword; and generating a second codeword based at least in part on a combination of the first codeword and the nested codeword. Integrated-interleaved LDPC decoding is also provided.
Abstract translation: 提供了用于集成交织的低密度奇偶校验（LDPC）编码和解码的方法和装置。 通过获得至少第一数据元素和第二数据元素来执行集成交错LDPC编码; 使用稀疏奇偶校验矩阵H1的子矩阵H0对所述至少第一数据元素进行系统地编码以获得至少第一码字; 截断所述至少第一数据元素以获得至少第一截断数据元素; 使用稀疏奇偶校验矩阵H1对所述至少第二数据元素和所述至少第一截断数据元素进行系统地编码以获得嵌套代码字; 以及至少部分地基于所述第一码字和所述嵌套码字的组合来生成第二码字。 还提供了集成交错LDPC解码。
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