公开(公告)号：US20110133304A1

公开(公告)日：2011-06-09

申请号：US12980268

申请日：2010-12-28

申请人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

发明人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

IPC分类号： H01L29/00 ,  H01L21/66

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

摘要翻译： 芯片包括多个层中的多个功能区域和该层内的多个虚设结构。 虚拟结构与功能区域间隔开。 每个虚拟结构具有作为功能区域的大小和密度的函数的大小。

公开(公告)号：US07868427B2

公开(公告)日：2011-01-11

申请号：US12353193

申请日：2009-01-13

申请人： Sebastian Schmidt ,  Hang-Yip Liu ,  Thomas Schafbauer ,  Yayi Wei

发明人： Sebastian Schmidt ,  Hang-Yip Liu ,  Thomas Schafbauer ,  Yayi Wei

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L21/302 ,  H01L23/544

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

摘要翻译： 正在处理的衬底上的材料层，例如， 以形成芯片，包括一个或多个功能结构。 为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。 特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

公开(公告)号：US20090124027A1

公开(公告)日：2009-05-14

申请号：US12353193

申请日：2009-01-13

申请人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

发明人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

IPC分类号： H01L21/66

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

摘要翻译： 正在处理的衬底上的材料层，例如， 以形成芯片，包括一个或多个功能结构。 为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。 特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

公开(公告)号：US07494930B2

公开(公告)日：2009-02-24

申请号：US11441649

申请日：2006-05-26

申请人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

发明人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

IPC分类号： H01L21/302

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

摘要翻译： 正在处理的衬底上的材料层，例如， 以形成芯片，包括一个或多个功能结构。 为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。 特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

公开(公告)号：US07071074B2

公开(公告)日：2006-07-04

申请号：US10671123

申请日：2003-09-24

申请人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

发明人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Yip Liu ,  Yayi Wei

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

公开(公告)号：US20050064634A1

公开(公告)日：2005-03-24

申请号：US10671123

申请日：2003-09-24

申请人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Liu ,  Yayi Wei

发明人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Liu ,  Yayi Wei

IPC分类号： G06F17/50 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/762 ,  H01L21/82 ,  H01L21/338 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

摘要翻译： 正在处理的衬底上的材料层，例如， 以形成芯片，包括一个或多个功能结构。 为了在制造芯片期间控制图案密度，将不同尺寸和形状的虚拟填充结构添加到与材料层的功能结构不同距离的芯片。 特别地，虚拟结构的布置，尺寸和形状被确定为材料层的功能结构的距离和密度的函数。

公开(公告)号：US20060216905A1

公开(公告)日：2006-09-28

申请号：US11441649

申请日：2006-05-26

申请人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Liu ,  Yayi Wei

发明人： Sebastian Schmidt ,  Thomas Schafbauer ,  Hang Liu ,  Yayi Wei

IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L21/461

CPC分类号： H01L22/10 ,  B81C1/00539 ,  G06F17/5068 ,  H01L21/027 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L21/82

摘要： A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer.

公开(公告)号：US06828647B2

公开(公告)日：2004-12-07

申请号：US09826732

申请日：2001-04-05

申请人： Thomas Schafbauer ,  Andreas Von Ehrenwall ,  Tobias Mono

发明人： Thomas Schafbauer ,  Andreas Von Ehrenwall ,  Tobias Mono

IPC分类号： H01L2900

CPC分类号： H01L22/34

摘要： A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

摘要翻译： 一种用于在半导体晶片中电气确定在形成阱之前包括在晶片中形成的绝缘层下方的阱的边缘的位置，并且绝缘层的多个导电条将在未来的绝缘层下方通过， 在绝缘层下方延伸到不同的距离，以便包括将穿透要被定位的边缘的条纹，以便形成与其抵抗的低电阻连接，并且将会落在不会被定位的边缘的条纹上。 从可以确定井边的位置的低阻力的最小穿透条纹。

公开(公告)号：US06815317B2

公开(公告)日：2004-11-09

申请号：US10164243

申请日：2002-06-05

申请人： Thomas Schafbauer ,  Sandrine E. Sportouch

发明人： Thomas Schafbauer ,  Sandrine E. Sportouch

IPC分类号： H01L2104

CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L21/266

摘要： A method of fabricating an integrated circuit in and on a semiconductor substrate with deep implantations by applying a scattered ion capturing layer in the resist mask opening to capture any implanted ions scattered in the resist and deflected out of the resist into the mask opening to prevent these ions from reaching the semiconductor substrate and affecting the concentration of ions at the edge of the mask and thus the performance of the integrated circuit.

公开(公告)号：US07268383B2

公开(公告)日：2007-09-11

申请号：US10370535

申请日：2003-02-20

申请人： Petra Felsner ,  Thomas Schafbauer ,  Uwe Kerst ,  Hans-Joachim Barth ,  Erdem Kaltalioglu

发明人： Petra Felsner ,  Thomas Schafbauer ,  Uwe Kerst ,  Hans-Joachim Barth ,  Erdem Kaltalioglu

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01G4/228 ,  H01G4/33 ,  H01L21/76838 ,  H01L27/0233 ,  H01L27/1085 ,  Y10T29/417

摘要： Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.

摘要翻译： 具有由高k电介质形成的电容器和在电介质两侧的一对互连件的半导体器件与制造这种半导体器件的方法一起提供。 互连包括通孔和金属层。