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公开(公告)号：US20200295746A1
公开(公告)日：2020-09-17
申请号：US16813839
申请日：2020-03-10
IPC分类号： H03K17/0812 , G05F1/56 , H03K17/00
摘要： Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.
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2.发明申请CONTROL APPARATUS, ELECTRO-OPTICAL APPARATUS, ELECTRONIC DEVICE, AND CONTROL METHOD 审中-公开控制装置，电光装置，电子装置和控制方法公开(公告)号：US20140247290A1
公开(公告)日：2014-09-04
申请号：US14193942
申请日：2014-02-28
CPC分类号： G09G3/344 , G09G2300/08 , G09G2310/061 , G09G2340/16
摘要： In order to achieve a desired gray level in an optical state of a bi-stable display element, voltage application is carried out so that the gray level follows a predetermined gray level change loop through a erasing period, a reset period, and a write period.
摘要翻译： 为了在双稳态显示元件的光学状态下实现期望的灰度级，执行电压施加，使得灰度级通过擦除周期，复位周期和写入周期遵循预定的灰度级改变环路 。
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公开(公告)号：US20190068408A1
公开(公告)日：2019-02-28
申请号：US16114550
申请日：2018-08-28
IPC分类号： H04L25/02 , H03K19/0175 , H04L25/03 , G06F13/40 , H04L7/04
CPC分类号： H04L25/0282 , G06F13/4072 , H03K19/0175 , H04L7/048 , H04L25/0292 , H04L25/03
摘要： A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.
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4.发明申请Integrated Circuit Device, Electronic Apparatus, And Control Method For Electrooptic Panel 有权集成电路器件，电子设备和电光板控制方法公开(公告)号：US20150371602A1
公开(公告)日：2015-12-24
申请号：US14737869
申请日：2015-06-12
发明人： Kota MUTO , Toshimichi YAMADA
CPC分类号： G09G3/04 , G09G3/344 , G09G5/18 , G09G2230/00 , G09G2310/08 , G09G2320/0276 , G09G2320/041 , G09G2370/08
摘要： An integrated circuit device includes: a timing information storage section that stores phase length information in correspondence with an index number; a waveform information storage section that stores waveform information related to a plurality of drive waveforms used in response to at least one display state; a timing control section that reads an index number included for each phase in the waveform information, reads phase length information corresponding to the index number from the timing information storage section, and sequentially generates a selection signal during a drive voltage application period corresponding to a plurality of phases; and a drive waveform selection section that selects a waveform value representing a drive voltage, out of a plurality of units of waveform information stored in the waveform information storage section, in accordance with the selection signal.
摘要翻译： 集成电路装置包括：定时信息存储部，其存储与索引号对应的相位长度信息; 波形信息存储部，其存储与响应于至少一个显示状态而使用的多个驱动波形有关的波形信息; 读取波形信息中的各相位的索引号的定时控制部从时刻信息存储部读取与该索引号相对应的相位长度信息，并且在与多个对应的驱动电压施加期间顺序地生成选择信号 的阶段; 以及驱动波形选择部，根据选择信号，从存储在波形信息存储部中的波形信息的多个单位中选择表示驱动电压的波形值。
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公开(公告)号：US20230311481A1
公开(公告)日：2023-10-05
申请号：US18192305
申请日：2023-03-29
发明人： Toshimichi YAMADA
CPC分类号： B41J2/04508 , B41J2/04513 , B41J2/04581 , G06F3/1232
摘要： A liquid discharge system including a piezoelectric element that is displaced in accordance with a drive signal and discharges liquid; a drive signal output circuit that outputs the drive signal; a measurement circuit that measures a first capacitance of the piezoelectric element; and a determination circuit that determines a deterioration state of the piezoelectric element based on the first capacitance.
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公开(公告)号：US20190303332A1
公开(公告)日：2019-10-03
申请号：US16367858
申请日：2019-03-28
发明人： Toshimichi YAMADA
摘要： A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard on in a first period and off in a second period, and a processing circuit that performs, in the second period, packet transfer processing on a transfer route that includes the first bus, the first and second physical layer circuits, the second bus. The bus switch circuit includes a first switch circuit, a second switch circuit, and a signal line connected between the first switch circuit and the second switch circuit.
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7.发明申请CONTROL APPARATUS, ELECTRO-OPTIC APPARATUS, ELECTRONIC DEVICE, AND CONTROL METHOD 审中-公开控制装置，电光装置，电子装置和控制方法公开(公告)号：US20140285479A1
公开(公告)日：2014-09-25
申请号：US14191968
申请日：2014-02-27
IPC分类号： G09G5/00
CPC分类号： G09G3/344 , G09G2310/068 , G09G2320/0252 , G09G2320/0257
摘要： In a refresh period, a voltage for alternatingly inverting a memory display element between a first gray level and a second gray level is applied. The number of inversions in the refresh period when the temperature of the memory display element is low is lower than the number of inversions in the refresh period when the temperature of the memory display element is high.
摘要翻译： 在刷新周期中，施加用于在第一灰度级和第二灰度级之间交替反转存储器显示元件的电压。 当存储器显示元件的温度低时，刷新周期中的反转次数低于当存储器显示元件的温度高时的刷新周期中的反转次数。
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公开(公告)号：US20190303331A1
公开(公告)日：2019-10-03
申请号：US16367485
申请日：2019-03-28
发明人： Toshimichi YAMADA
摘要： A circuit device includes first and second physical layer circuits, a bus switch circuit that switches connection between a first bus and a second bus that comply with a USB standard, on in a first period and off in a second period, and a processing circuit that performs, in the second period, processing for transferring packets on a transfer route that includes the first bus, the first and second physical layer circuits, and the second bus. When a host chirp K/J is detected on the first bus by the first physical layer circuit, the second physical layer circuit outputs a host chirp K/J to the second bus in the state where connection between the first bus and the second bus is switched off by the bus switch circuit.
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公开(公告)号：US20180351544A1
公开(公告)日：2018-12-06
申请号：US15969655
申请日：2018-05-02
发明人： Kota MUTO , Toshimichi YAMADA
摘要： A circuit device includes: a transmitting circuit that performs transmission of a signal by current-driving signal lines in a transmission period; a receiving circuit that receives a signal that a transmitting circuit of a communication partner has transmitted by current-driving the signal lines, in a reception period that is different from the transmission period; and terminating resistor circuits that can be connected to the signal lines, and whose resistance value in the transmission period is set to a value that is smaller than a resistance value in the reception period.
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公开(公告)号：US20180212796A1
公开(公告)日：2018-07-26
申请号：US15876973
申请日：2018-01-22
CPC分类号： H04L12/40078 , G01R31/007 , G01R31/041 , G06F1/06 , G06F11/00 , G06F13/4022 , H03L7/16 , H04L12/64
摘要： A circuit device includes: a first physical layer circuit to which a first bus compliant with a USB standard is connected; a second physical layer circuit to which a second bus compliant with the USB standard is connected; a processing circuit that performs transfer processing in which a packet received from the first bus via the first physical layer circuit is transferred to the second bus via the second physical layer circuit, and a packet received from the second bus via the second physical layer circuit is transferred to the first bus via the first physical layer circuit; a bus monitor circuit that performs a monitor operation with respect to the first and second buses; and a bus switch circuit that switches on or off a connection between the first bus and the second bus based on a monitor result from the bus monitor circuit.
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