公开(公告)号：US11342443B2

公开(公告)日：2022-05-24

申请号：US16833237

申请日：2020-03-27

Applicant: Semiconductor Components Industries, LLC

Inventor： Peter Moens ,  Abhishek Banerjee

IPC: H01L29/66 ,  H01L29/32 ,  H01L29/778 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/20

Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.

公开(公告)号：US10276713B2

公开(公告)日：2019-04-30

申请号：US15487517

申请日：2017-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/10 ,  H01L29/778 ,  H01L21/74 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L29/417 ,  H01L21/76 ,  H01L21/763 ,  H01L21/02

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US10062756B2

公开(公告)日：2018-08-28

申请号：US14867131

申请日：2015-09-28

Applicant: Semiconductor Components Industries, LLC

Inventor： Peter Moens

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/207

CPC classification number: H01L29/1075 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/404 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×1015 atoms/cm3.

公开(公告)号：US09960265B1

公开(公告)日：2018-05-01

申请号：US15422764

申请日：2017-02-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek Banerjee ,  Peter Moens ,  Gordon M. Grivna

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/02175 ,  H01L21/02107 ,  H01L21/02241 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66462 ,  H01L29/7786

Abstract: In one embodiment, a III-V high electron mobility semiconductor device includes a semiconductor substrate including a GaN layer, an AlGaN layer on the GaN layer wherein a 2 DEG is formed near an interface of the GaN layer and the AlGaN layer. An insulator may be on at least a first portion of the AlGaN layer and a P-type GaN gate region may be overlying a second portion of the AlGaN layer wherein the 2 DEG does not underlie the P-type GaN gate region.

公开(公告)号：US09515179B2

公开(公告)日：2016-12-06

申请号：US14690703

申请日：2015-04-20

Applicant: Semiconductor Components Industries, LLC

Inventor： Peter Moens ,  Piet Vanmeerbeek ,  John Michael Parsey, Jr.

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7827 ,  H01L21/28264 ,  H01L29/0603 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66522 ,  H01L29/66666

Abstract: An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.

Abstract translation: 电子器件可以包括具有栅电极和同构结构内的沟道区的垂直III-V晶体管。 沟道区可以设置在栅电极的第一部分和第二部分之间。 在一个实施例中，III-V晶体管可以是增强型GaN晶体管，并且在特定实施例中，漏极，源极和沟道区域可以包括相同的导电类型。

公开(公告)号：US09324784B2

公开(公告)日：2016-04-26

申请号：US14249677

申请日：2014-04-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Jaume Roig Guitart ,  Zia Hossain ,  Peter Moens

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/36 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/06 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/40 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract translation: 电子设备可以包括电子部件和与电子部件区域相邻的端接区域。 在一个实施例中，终端区域可以包括将深度延伸到半导体层中的绝缘区域，其中深度小于半导体层厚度的50％。 在另一个实施例中，终端区域可以包括将第一深度延伸到半导体层中的第一绝缘区域和将第二深度延伸到半导体层中的第二绝缘区域，其中第二深度小于第一深度。 在另一方面，形成电子器件的工艺可以包括图案化半导体层以限定终止区域内的沟槽，同时为电子部件区域内的电子部件形成另一个沟槽。

公开(公告)号：US12183785B2

公开(公告)日：2024-12-31

申请号：US18340650

申请日：2023-06-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter Moens ,  Gordon M. Grivna ,  Yusheng Lin

IPC: H01L29/06 ,  H01L21/762 ,  H01L25/07 ,  H01L29/20

Abstract: In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

公开(公告)号：US20210005740A1

公开(公告)日：2021-01-07

申请号：US16948517

申请日：2020-09-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Abhishek Banerjee ,  Peter Moens

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/51 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.

公开(公告)号：US10090380B2

公开(公告)日：2018-10-02

申请号：US15009380

申请日：2016-01-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter Moens ,  Ana Villamor ,  Piet Vanmeerbeek ,  Jaume Roig-Guitart ,  Filip Bogman

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/36 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739 ,  H01L21/76

Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.

公开(公告)号：US20180012995A1

公开(公告)日：2018-01-11

申请号：US15695231

申请日：2017-09-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Zia Hossain ,  Juraj Vavro ,  Peter Moens

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811

Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.