公开(公告)号：US20190185986A1

公开(公告)日：2019-06-20

申请号：US16285297

申请日：2019-02-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC: C23C14/08 ,  C23C14/34 ,  H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  C04B35/453 ,  B28B11/24 ,  C04B35/64

CPC classification number: C23C14/08 ,  B28B11/243 ,  C04B35/453 ,  C04B35/64 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/76 ,  C23C14/086 ,  C23C14/3414 ,  C23C14/345 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

公开(公告)号：US20180277392A1

公开(公告)日：2018-09-27

申请号：US15991080

申请日：2018-05-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuhei SATO ,  Keiji SATO ,  Tetsunori MARUYAMA ,  Junichi KOEZUKA

IPC: H01L21/40 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L21/383 ,  H01L21/477 ,  H01L27/12

CPC classification number: H01L21/40 ,  H01L21/02175 ,  H01L21/02252 ,  H01L21/02565 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/383 ,  H01L21/477 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.

公开(公告)号：US20170016108A1

公开(公告)日：2017-01-19

申请号：US15189104

申请日：2016-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC: C23C14/08 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  C23C14/34 ,  H01L21/02

CPC classification number: C23C14/08 ,  B28B11/243 ,  C04B35/453 ,  C04B35/64 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/76 ,  C23C14/086 ,  C23C14/3414 ,  C23C14/345 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

Abstract translation: 已经有使用氧化物半导体形成的晶体管的可靠性与使用非晶硅形成的晶体管的可靠性差。 因此，在本发明中，制造了包括使用氧化物半导体形成的高可靠性晶体管的半导体器件。 使用包含具有结晶性的氧化物半导体的溅射靶，通过溅射法沉积氧化物半导体膜，并且其中晶体的c轴方向平行于氧化物半导体的顶表面的法向矢量。 通过混合原料形成靶，使其组成比可以得到晶体结构。

公开(公告)号：US20220037532A1

公开(公告)日：2022-02-03

申请号：US17504923

申请日：2021-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoshi TORIUMI ,  Takashi HAMADA ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Yuji ASANO ,  Ryunosuke HONDA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/51 ,  H01L29/49 ,  H01L29/417 ,  H01L27/12 ,  H01L27/146 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/423 ,  H01L21/822

Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.

公开(公告)号：US20170243899A1

公开(公告)日：2017-08-24

申请号：US15591145

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Yuichi SATO ,  Yuji ASANO ,  Tetsunori MARUYAMA ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/485 ,  H01L23/522 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/786 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L27/1225 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

公开(公告)号：US20170025448A1

公开(公告)日：2017-01-26

申请号：US15285661

申请日：2016-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun KOYAMA ,  Junichiro SAKATA ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Yuji ASANO ,  Junichi KOEZUKA

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/127 ,  H01L28/20 ,  H01L29/24 ,  H01L29/78606 ,  H01L29/7869

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

Abstract translation: 通过使用含有氢化合物如硅烷（SiH 4）和氨（NH 3）的气体的等离子体CVD形成的氮化硅层910设置在与用于电阻器354的氧化物半导体层905上并直接接触，并且氮化硅 在用于薄膜晶体管355的氧化物半导体层906上设置层910，氧化硅层909用作阻挡层。 因此，与氧化物半导体层906相比，在氧化物半导体层905中引入更高浓度的氢。结果，使用于电阻器354的氧化物半导体层905的电阻比氧化物半导体层的电阻低 906用于薄膜晶体管355。

公开(公告)号：US20160276370A1

公开(公告)日：2016-09-22

申请号：US15072076

申请日：2016-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Yuichi SATO ,  Yuji ASANO ,  Tetsunori MARUYAMA ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/16 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H01L23/522

CPC classification number: H01L27/1225 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

Abstract translation: 提供具有优异电气特性的半导体器件或具有稳定电特性的半导体器件。 半导体器件包括第一晶体管，第二晶体管，第一绝缘体，第二绝缘体，第一布线和第一插塞。 第一晶体管包括硅。 第二晶体管包括氧化物半导体。 第一绝缘体位于第一晶体管的上方。 第二绝缘体位于第一绝缘体之上。 第二晶体管位于第二绝缘体上。 第一布线位于第二绝缘体和第一插头上。 第一晶体管和第二晶体管通过第一布线和第一插头彼此电连接。 第一布线具有低的透气性。 第二绝缘体的氢渗透性低于第一绝缘体的氢渗透性。

公开(公告)号：US20130133808A1

公开(公告)日：2013-05-30

申请号：US13677656

申请日：2012-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA

IPC: C23C14/08

CPC classification number: C23C14/08 ,  C04B35/01 ,  C04B35/453 ,  C04B35/6262 ,  C04B35/645 ,  C04B35/6455 ,  C04B37/02 ,  C04B2235/3232 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3287 ,  C04B2235/3293 ,  C04B2235/6583 ,  C04B2235/6585 ,  C04B2235/666 ,  C04B2235/94 ,  C04B2237/34 ,  C04B2237/403 ,  C04B2237/406 ,  C04B2237/407 ,  C23C14/3414 ,  H01L21/02

Abstract: When an oxide semiconductor is deposited by a sputtering method, there is a difference in composition between a sputtering target and a film deposited using the sputtering target in some cases depending on a material of the oxide semiconductor. In manufacturing a sputtering target containing zinc oxide, a crystal which contains zinc oxide is formed in advance, the crystal is crushed, and then a predetermined amount of zinc oxide is added and mixed. After that, the resulting object is sintered to form the sputtering target. The composition of the sputtering target is adjusted by setting the proportion of zinc in the sputtering target higher than that of zinc in a film having a desired composition which is obtained at last, in consideration of the amount of zinc which is reduced at the time of deposition by a sputtering method, the amount of zinc which is reduced at the time of sintering, and the like.

Abstract translation: 当通过溅射法沉积氧化物半导体时，根据氧化物半导体的材料，在某些情况下，溅射靶和使用溅射靶沉积的膜之间的组成存在差异。 在制造含有氧化锌的溅射靶时，预先形成含有氧化锌的结晶，将晶体粉碎，然后加入预定量的氧化锌并混合。 之后，将所得到的物体烧结以形成溅射靶。 通过将溅射靶中锌的比例设定为具有最终获得的所需组成的膜中的锌的比例，考虑到在 通过溅射法沉积，烧结时减少的锌的量等。

公开(公告)号：US20250146126A1

公开(公告)日：2025-05-08

申请号：US19018112

申请日：2025-01-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Hitomi SATO ,  Masahiro WATANABE ,  Mitsuo MASHIYAMA ,  Kenichi OKAZAKI ,  Motoki NAKASHIMA ,  Takashi SHIMAZU

IPC: C23C14/34 ,  B28B11/24 ,  C04B35/453 ,  C04B35/64 ,  C23C14/08 ,  H01L21/02 ,  H10D30/67 ,  H10D62/80 ,  H10D99/00

Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.

公开(公告)号：US20160300952A1

公开(公告)日：2016-10-13

申请号：US15091009

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoshi TORIUMI ,  Takashi HAMADA ,  Tetsunori MARUYAMA ,  Yuki IMOTO ,  Yuji ASANO ,  Ryunosuke HONDA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/51 ,  H01L27/105 ,  H01L29/417 ,  H01L27/12 ,  H01L29/24 ,  H01L29/49

Abstract: A minute transistor is provided. A semiconductor device includes a semiconductor over a substrate, a first conductor and a second conductor over the semiconductor, a first insulator over the first conductor and the second conductor, a second insulator over the semiconductor, a third insulator over the second insulator, and a third conductor over the third insulator. The third insulator is in contact with a side surface of the first insulator. The semiconductor includes a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between a top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.

Abstract translation: 提供一分钟晶体管。 半导体器件包括衬底上的半导体，半导体上的第一导体和第二导体，第一导体和第二导体上的第一绝缘体，半导体上的第二绝缘体，第二绝缘体上的第三绝缘体，以及 第三绝缘体上的第三导体。 第三绝缘体与第一绝缘体的侧表面接触。 半导体包括半导体与第一导体的底表面重叠的第一区域，半导体与第二导体的底表面重叠的第二区域和半导体与第三导体的底表面重叠的第三区域 导体。 半导体的顶表面和第三导体的底表面之间的长度比第一区域和第三区域之间的长度长。