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公开(公告)号：US11348653B2
公开(公告)日：2022-05-31
申请号：US16458304
申请日：2019-07-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Kouhei Toyotaka , Hiroyuki Miyake , Aya Miyazaki , Hideaki Shishido , Koji Kusunoki
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US10181359B2
公开(公告)日：2019-01-15
申请号：US14921073
申请日：2015-10-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki Miyake , Seiko Amano
IPC: G11C19/28 , G09G3/3266 , G09G3/36
Abstract: The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.
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公开(公告)号：US08693617B2
公开(公告)日：2014-04-08
申请号：US13891364
申请日：2013-05-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Kouhei Toyotaka , Hiroyuki Miyake , Aya Miyazaki , Hideaki Shishido , Koji Kusunoki
IPC: G11C19/00
CPC classification number: G11C19/28 , G09G3/3677 , G09G3/3696 , G09G2300/0809 , G09G2310/0286 , G11C19/184 , H01L25/03 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L27/1288 , H01L2924/0002 , H03K19/0013 , H05K7/02 , H01L2924/00
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
Abstract translation: 目的在于提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。 根据所公开的发明的一个实施例的脉冲信号输出电路包括第一至第十晶体管。 沟道宽度W与第一晶体管的沟道长度L和第三晶体管的W / L的比率W / L都大于第六晶体管的W / L。 第五晶体管的W / L大于第六晶体管的W / L。 第五晶体管的W / L等于第七晶体管的W / L。 第三晶体管的W / L大于第四晶体管的W / L。 通过这样的结构，可以提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。
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公开(公告)号：US11942170B2
公开(公告)日：2024-03-26
申请号：US17749309
申请日：2022-05-20
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Kouhei Toyotaka , Hiroyuki Miyake , Aya Miyazaki , Hideaki Shishido , Koji Kusunoki
CPC classification number: G11C19/28 , G09G3/3677 , G09G3/3696 , G11C19/184 , H01L25/03 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L27/1288 , H03K19/0013 , H05K7/02 , G09G2300/0809 , G09G2310/0286 , H01L2924/0002 , H01L2924/0002 , H01L2924/00
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US11468860B2
公开(公告)日：2022-10-11
申请号：US17458656
申请日：2021-08-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Hiroyuki Miyake
IPC: G09G3/36 , G06F3/038 , G09G3/3266 , G11C19/28 , G06F1/3234 , H01L27/12 , G09G5/00
Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
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Patent Agency Ranking
公开(公告)号：US11107432B2
公开(公告)日：2021-08-31
申请号：US17073634
申请日：2020-10-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Hiroyuki Miyake
IPC: G09G3/32 , G09G3/36 , G11C19/28 , G06F3/038 , G09G3/3266 , G06F1/3234 , H01L27/12 , G09G5/00
Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
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公开(公告)号：US20140301045A1
公开(公告)日：2014-10-09
申请号：US14245097
申请日：2014-04-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Kouhei Toyotaka , Hiroyuki Miyake , Aya Miyazaki , Hideaki Shishido , Koji Kusunoki
CPC classification number: G11C19/28 , G09G3/3677 , G09G3/3696 , G09G2300/0809 , G09G2310/0286 , G11C19/184 , H01L25/03 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L27/1288 , H01L2924/0002 , H03K19/0013 , H05K7/02 , H01L2924/00
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
Abstract translation: 目的在于提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。 根据所公开的发明的一个实施例的脉冲信号输出电路包括第一至第十晶体管。 沟道宽度W与第一晶体管的沟道长度L和第三晶体管的W / L的比W / L分别大于第六晶体管的W / L。 第五晶体管的W / L大于第六晶体管的W / L。 第五晶体管的W / L等于第七晶体管的W / L。 第三晶体管的W / L大于第四晶体管的W / L。 通过这样的结构，可以提供能够稳定运行的脉冲信号输出电路和包括脉冲信号输出电路的移位寄存器。
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公开(公告)号：US10818256B2
公开(公告)日：2020-10-27
申请号：US15393389
申请日：2016-12-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Hiroyuki Miyake
IPC: G09G3/36 , G06F1/32 , G11C19/28 , H01L27/12 , G06F3/038 , G09G3/3266 , G06F1/3234 , G09G5/00
Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
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公开(公告)号：US10340021B2
公开(公告)日：2019-07-02
申请号：US15203885
申请日：2016-07-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko Amano , Kouhei Toyotaka , Hiroyuki Miyake , Aya Miyazaki , Hideaki Shishido , Koji Kusunoki
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US09704940B2
公开(公告)日：2017-07-11
申请号：US15162667
申请日：2016-05-24
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiko Amano
CPC classification number: H01L27/3276 , H01L27/1214 , H01L27/1244 , H01L27/3262 , H01L51/5246 , H01L51/5253 , H01L2251/5338 , H05B33/04
Abstract: It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.
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