公开(公告)号：US08921169B2

公开(公告)日：2014-12-30

申请号：US13890293

申请日：2013-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract translation: 为了形成栅电极，层叠具有低电阻的包含Al或以Al为主要成分的材料的导电膜和用于防止Al扩散到半导体层中的具有低接触电阻的导电膜，并且栅电极由 使用能够高速进行蚀刻处理的装置。

公开(公告)号：US20140256116A1

公开(公告)日：2014-09-11

申请号：US14285718

申请日：2014-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC: H01L21/48 ,  H01L21/02

CPC classification number: H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

Abstract translation: 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US20130252385A1

公开(公告)日：2013-09-26

申请号：US13890293

申请日：2013-05-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC: H01L29/66

CPC classification number: H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

公开(公告)号：US09330940B2

公开(公告)日：2016-05-03

申请号：US14285718

申请日：2014-05-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Yoshihiro Kusuyama ,  Koji Ono ,  Jun Koyama

IPC: H01L21/48 ,  G02F1/1345 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L21/4846 ,  G02F1/13454 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L21/02367 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1277 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78621 ,  H01L29/78627

Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more.

Abstract translation: 提供了即使在将显示区域的尺寸增加到大尺寸屏幕的情况下也实现低功耗的半导体器件的结构及其制造方法。 像素部分中的栅电极形成为主要包含W的材料膜，主要包含Al的材料膜和主要包含Ti的材料膜以降低布线电阻的三层结构。 使用IPC蚀刻装置蚀刻布线。 栅电极为锥形，成为锥形的区域的宽度为1μm以上。

公开(公告)号：US09142574B2

公开(公告)日：2015-09-22

申请号：US14571424

申请日：2014-12-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC: H01L21/64 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3213

CPC classification number: H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

公开(公告)号：US20150099333A1

公开(公告)日：2015-04-09

申请号：US14571424

申请日：2014-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Koji Ono ,  Yoshihiro Kusuyama

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3213

CPC classification number: H01L27/1296 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L2029/7863

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract translation: 为了形成栅电极，层叠具有低电阻的包含Al或以Al为主要成分的材料的导电膜和用于防止Al扩散到半导体层中的具有低接触电阻的导电膜，并且栅电极由 使用能够高速进行蚀刻处理的装置。