公开(公告)号：US08872259B2

公开(公告)日：2014-10-28

申请号：US13445798

申请日：2012-04-12

申请人： Seung Hwan Kim ,  Jai Hoon Sim

发明人： Seung Hwan Kim ,  Jai Hoon Sim

IPC分类号： H01L29/66 ,  H01L27/108 ,  H01L27/02

CPC分类号： H01L27/10823 ,  H01L27/0218 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/42364

摘要： A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

摘要翻译： 提供半导体器件及其制造方法，以防止浮体效应并降低掩埋位线之间的耦合电容。 半导体器件包括设置在半导体衬底上并包括垂直沟道区的第一柱，位于第一柱内部的垂直沟道区的下部的位线和从半导体衬底延伸至半导体衬底的一个侧壁的半导体层 第一支柱

公开(公告)号：US20130105872A1

公开(公告)日：2013-05-02

申请号：US13445798

申请日：2012-04-12

申请人： Seung Hwan KIM ,  Jai Hoon Sim

发明人： Seung Hwan KIM ,  Jai Hoon Sim

IPC分类号： H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/0218 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/4236 ,  H01L29/42364

摘要： A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

公开(公告)号：US07541241B2

公开(公告)日：2009-06-02

申请号：US11298836

申请日：2005-12-12

申请人： Jai Hoon Sim ,  Jih Wen Chou

发明人： Jai Hoon Sim ,  Jih Wen Chou

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/41783 ,  H01L29/66553 ,  H01L29/66621

摘要： A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

摘要翻译： 存储单元结构包括半导体衬底，位于半导体衬底上的两个堆叠结构，位于两个堆叠结构的侧壁上的两个导电间隔物，覆盖两个导电间隔物之间​​的半导体衬底的一部分的栅极氧化物层和栅极结构 至少位于栅极氧化物层上。 特别地，两个堆叠结构中的每一个包括第一氧化物块，导电块和第二氧化物块，并且两个导电间隔物位于两个堆叠结构的两个导电块的侧壁上。 两个导电间隔物优选由多晶硅制成，并且具有比第二氧化物块的底表面低的顶端。 此外，介电隔离物位于两个导电间隔物中的每一个上。

公开(公告)号：US20110170336A1

公开(公告)日：2011-07-14

申请号：US12856481

申请日：2010-08-13

申请人： Jai Hoon Sim

发明人： Jai Hoon Sim

IPC分类号： G11C11/24 ,  H01L21/8242

CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

摘要： The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.

摘要翻译： 本发明涉及具有4F2尺寸单元的DRAM器件及其制造方法。 DRAM装置包括在一个方向上彼此平行布置的多个字线，彼此平行并与字线交叉排列的多个位线，以及多个存储单元，具有晶体管和与源极端子电连接的电容器 的晶体管。 晶体管的栅极端子以位线方向填充两个相邻的存储单元之间的相关联的沟槽，并且经由插入在栅极端子和所述两个相邻存储器单元之间的栅极绝缘膜同时覆盖所述两个相邻存储单元的侧壁。 位或字线方向上的栅极端子之间的间隔比1F更远，F表示最小的处理尺寸。

公开(公告)号：US08467220B2

公开(公告)日：2013-06-18

申请号：US12856481

申请日：2010-08-13

申请人： Jai Hoon Sim

发明人： Jai Hoon Sim

IPC分类号： G11C5/06 ,  G11C11/24 ,  H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

摘要： The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.

摘要翻译： 本发明涉及具有4F2尺寸单元的DRAM器件及其制造方法。 DRAM装置包括在一个方向上彼此平行布置的多个字线，彼此平行并与字线交叉排列的多个位线，以及多个存储单元，具有晶体管和与源极端子电连接的电容器 的晶体管。 晶体管的栅极端子以位线方向填充两个相邻的存储单元之间的相关联的沟槽，并且经由插入在栅极端子和所述两个相邻存储器单元之间的栅极绝缘膜同时覆盖所述两个相邻存储单元的侧壁。 位或字线方向上的栅极端子之间的间隔比1F更远，F表示最小的处理尺寸。