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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
    三维半导体存储器件

    公开(公告)号：US20170047343A1

    公开(公告)日：2017-02-16

    申请号：US15208669

    申请日：2016-07-13

    申请人： Dohyun LEE ,  Younghwan SON ,  Minyeong SONG ,  YOUNGWOO PARK ,  Jaeduk LEE

    发明人： Dohyun LEE ,  Younghwan SON ,  Minyeong SONG ,  YOUNGWOO PARK ,  Jaeduk LEE

    IPC分类号： H01L27/115 ,  G11C16/08 ,  G11C16/26 ,  H01L29/167 ,  G11C16/10

    CPC分类号： H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/167

    摘要： Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.

    摘要翻译： 提供一种三维半导体存储器件，其包括在半导体衬底上的外围逻辑结构，包括外围逻辑电路和下部绝缘间隙填充层，外围逻辑结构上的水平半导体层，堆叠在水平半导体层上， 包括垂直堆叠在水平半导体层上的多个电极的堆叠和穿过堆叠并连接到水平半导体层的多个垂直结构。 水平半导体层可以包括设置在下绝缘间隙填充层上并与反扩散材料共掺杂的第一半导体层和第一杂质浓度的第一导电型杂质，以及设置在第一半导体层上的第二半导体层， 掺杂具有低于第一杂质浓度的第二杂质浓度的第一导电型杂质或未掺杂的。

    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE 有权
    具有互连结构的半导体器件

    公开(公告)号：US20170011996A1

    公开(公告)日：2017-01-12

    申请号：US15201922

    申请日：2016-07-05

    申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

    IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

    CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

    摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。

    3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
    5.
    发明申请
    3-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
    三维半导体存储器件及其操作方法

    公开(公告)号：US20160343450A1

    公开(公告)日：2016-11-24

    申请号：US15157720

    申请日：2016-05-18

    申请人： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

    发明人： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

    IPC分类号： G11C16/34 ,  G11C16/04 ,  H01L29/16 ,  H01L23/528 ,  H01L29/04 ,  G11C16/10 ,  H01L27/115

    CPC分类号： H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

    摘要： Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

    摘要翻译： 公开了一种三维半导体存储器件，包括形成在第一衬底上的单元阵列和形成在第二衬底上的外围电路，所述外围电路至少部分地与第一衬底重叠，其中外围电路被配置为提供控制信号 单元格阵列。 电池阵列包括在第一衬底上交替堆叠的绝缘图案和栅极图案，以及至少第一柱，其沿垂直于第一衬底的方向形成，并且通过绝缘图案和栅极图案与第一衬底接触。 所述三维半导体存储器件还包括第一接地选择晶体管，其包括与所述第一衬底和所述第一柱相邻的第一栅极图案，以及第二接地选择晶体管，所述第二接地选择晶体管包括位于所述第一栅极图案上的第二栅极图案， 第一支柱，并且其中第一接地选择晶体管不可编程，并且第二接地选择晶体管是可编程的。