公开(公告)号：US20100229007A1

公开(公告)日：2010-09-09

申请号：US12711720

申请日：2010-02-24

申请人： Junghoon Park

发明人： Junghoon Park

IPC分类号： G06F12/14

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C2029/0409

摘要： An operating method of a non-volatile memory device includes randomizing source data to form randomized source data, storing the randomized source data, generating a seed based on an address, generating a random data sequence based on the seed, and de-randomizing the randomized data using the random data sequence. Related nonvolatile memory devices and methods of reading data stored in non-volatile memory devices are also disclosed.

摘要翻译： 非易失性存储器件的操作方法包括随机化源数据以形成随机化源数据，存储随机化源数据，基于地址生成种子，基于种子生成随机数据序列，以及将随机化的源数据去随机化 数据使用随机数据序列。 还公开了相关的非易失性存储器件和读取存储在非易失性存储器件中的数据的方法。

公开(公告)号：US09960171B2

公开(公告)日：2018-05-01

申请号：US15245540

申请日：2016-08-24

申请人： Kohji Kanamori ,  Shinhwan Kang ,  Youngwoo Park ,  Junghoon Park

发明人： Kohji Kanamori ,  Shinhwan Kang ,  Youngwoo Park ,  Junghoon Park

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.

公开(公告)号：US20170125428A1

公开(公告)日：2017-05-04

申请号：US15245540

申请日：2016-08-24

申请人： Kohji Kanamori ,  Shinhwan Kang ,  Youngwoo Park ,  Junghoon Park

发明人： Kohji Kanamori ,  Shinhwan Kang ,  Youngwoo Park ,  Junghoon Park

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.

公开(公告)号：US09025383B2

公开(公告)日：2015-05-05

申请号：US13650545

申请日：2012-10-12

申请人： Sang-Wan Nam ,  Junghoon Park

发明人： Sang-Wan Nam ,  Junghoon Park

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A method is provided for programming a nonvolatile memory device, which includes multiple memory cells connected in series in a direction substantially perpendicular to a substrate. The method includes programming a first memory cell of the multiple memory cells, and programming a second memory cell of the multiple memory cells after the first memory cell is programmed, the second memory cell being closer to the substrate than the first memory cell. A diameter of a channel hole of the first memory cell is larger than a diameter of a channel hole of the second memory cell.

摘要翻译： 提供一种用于对非易失性存储器件进行编程的方法，该非易失性存储器件包括在基本上垂直于衬底的方向上串联连接的多个存储器单元。 该方法包括编程多个存储器单元的第一存储单元，以及在编程第一存储单元之后对多个存储器单元的第二存储单元进行编程，第二存储单元比第一存储单元更靠近衬底。 第一存储单元的通道孔的直径大于第二存储单元的通道孔的直径。

公开(公告)号：US20130275658A1

公开(公告)日：2013-10-17

申请号：US13767535

申请日：2013-02-14

申请人： JINMAN HAN ,  HO-CHUL LEE ,  MIN-SU KIM ,  SANGWAN NAM ,  JUNGHOON PARK

发明人： JINMAN HAN ,  HO-CHUL LEE ,  MIN-SU KIM ,  SANGWAN NAM ,  JUNGHOON PARK

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11582

摘要： A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively.

摘要翻译： 提供一种用于编程闪存器件的方法，所述闪存器件包括沿垂直于衬底的方向形成的存储器单元，连接到第一存储器单元并由第一选择线选择的第一子字线以及连接到第二存储器的第二子字线 并且可由第二选择线选择，第一和第二存储器单元在同一电平上形成，同时被提供有编程电压。 该方法包括分别通过启用第一和第二选择线来对第一和第二子字线执行LSB编程操作; 通过分别启用第一和第二选择线来对第一和第二子字线执行CSB编程操作; 以及通过分别启用第一和第二选择线来对第一和第二子字线执行MSB编程操作。

公开(公告)号：US20130170297A1

公开(公告)日：2013-07-04

申请号：US13619118

申请日：2012-09-14

申请人： Sang-Wan NAM ,  Kyung-Hwa KANG ,  Junghoon PARK

发明人： Sang-Wan NAM ,  Kyung-Hwa KANG ,  Junghoon PARK

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11582

摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.

摘要翻译： 根据示例性实施例，非易失性存储器件包括第一和第二NAND串。 第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。 第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。 该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。 第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

公开(公告)号：US20130083599A1

公开(公告)日：2013-04-04

申请号：US13597534

申请日：2012-08-29

申请人： SANG-WAN NAM ,  WON-TAECK JUNG ,  JUNGHOON PARK

发明人： SANG-WAN NAM ,  WON-TAECK JUNG ,  JUNGHOON PARK

IPC分类号： G11C16/16

CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

摘要： An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

公开(公告)号：US20110273642A1

公开(公告)日：2011-11-10

申请号：US12903634

申请日：2010-10-13

申请人： Youngmin KWEON ,  Youngeun Lee ,  Junghoon Park

发明人： Youngmin KWEON ,  Youngeun Lee ,  Junghoon Park

IPC分类号： G02F1/1335 ,  F21V7/04

CPC分类号： G02F1/1336 ,  G02B6/0083 ,  G02B6/0088 ,  G02F2001/133612

摘要： A backlight unit and a liquid crystal display using the same are disclosed. The backlight unit includes a plurality of light sources generating light, a light source printed circuit board (PCB) on which the plurality of light sources are mounted, a protrusion that protrudes from one side of the light source PCB and is fastened to a connector used to supply a driving power to the plurality of light sources, and a bottom cover that receives the light source PCB and has a through hole through which the protrusion passes. The connector is exposed to the outside through the through hole.

摘要翻译： 公开了使用其的背光单元和液晶显示器。 背光单元包括产生光的多个光源，安装有多个光源的光源印刷电路板（PCB），从光源PCB的一侧突出并且被紧固到所使用的连接器的突起 以向多个光源提供驱动力，以及底盖，其接收光源PCB并具有突出部穿过的通孔。 连接器通过通孔暴露于外部。

公开(公告)号：US10418278B2

公开(公告)日：2019-09-17

申请号：US15857961

申请日：2017-12-29

申请人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/528

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US20170011996A1

公开(公告)日：2017-01-12

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。