APPARATUS AND METHOD FOR WRITING DATA TO PHASE-CHANGE MEMORY BY USING POWER CALCULATION AND DATA INVERSION
    7.
    发明申请
    APPARATUS AND METHOD FOR WRITING DATA TO PHASE-CHANGE MEMORY BY USING POWER CALCULATION AND DATA INVERSION 有权
    通过使用功率计算和数据反相将数据写入相变记忆的装置和方法

    公开(公告)号:US20080219047A1

    公开(公告)日:2008-09-11

    申请号:US12040137

    申请日:2008-02-29

    IPC分类号: G11C7/00 G11C11/21

    摘要: Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or inverted data is written to a PRAM and storing the data consuming less power. A PRAM consumes a significant amount of power in order to store data in a memory cell since a large electric current is required to flow for a long period of time. According to the present invention, since the PRAM consumes different amounts of power when writing data with a value of 0 and data with a value of 1, the power consumed when input original data is stored and the power consumed when the input original data is inverted and stored are compared to each other, the data with a smaller power consumption is stored when the data is written to the PRAM as a word unit, and thus the power consumption of the PRAM can be reduced.

    摘要翻译: 提供了一种通过使用写入功率计算和数据反转功能将数据写入相变随机存取存储器(PRAM)的装置和方法,更具体地,涉及一种用于写入数据的装置和方法,该装置和方法可通过计算功率来最小化功耗 在输入原始数据或反相数据被写入PRAM并存储消耗较少功率的数据时消耗。 由于需要大电流长时间流动,所以PRAM消耗大量的功率以便将数据存储在存储单元中。 根据本发明,由于在写入值为0的数据和值为1的数据时,PRAM消耗不同的功率量,所以当输入原始数据被存储时消耗的功率和当输入的原始数据被反相时消耗的功率 并将其进行存储,将数据作为字单元写入PRAM时,存储具有较小功耗的数据,从而能够降低PRAM的功耗。

    Apparatus and method for writing data to phase-change memory by using power calculation and data inversion
    8.
    发明授权
    Apparatus and method for writing data to phase-change memory by using power calculation and data inversion 有权
    通过使用功率计算和数据反演将数据写入相变存储器的装置和方法

    公开(公告)号:US07920413B2

    公开(公告)日:2011-04-05

    申请号:US12040137

    申请日:2008-02-29

    IPC分类号: G11C11/00

    摘要: Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or inverted data is written to a PRAM and storing the data consuming less power. A PRAM consumes a significant amount of power in order to store data in a memory cell since a large electric current is required to flow for a long period of time. According to the present invention, since the PRAM consumes different amounts of power when writing data with a value of 0 and data with a value of 1, the power consumed when input original data is stored and the power consumed when the input original data is inverted and stored are compared to each other, the data with a smaller power consumption is stored when the data is written to the PRAM as a word unit, and thus the power consumption of the PRAM can be reduced.

    摘要翻译: 提供了一种通过使用写入功率计算和数据反转功能将数据写入相变随机存取存储器(PRAM)的装置和方法,更具体地,涉及一种用于写入数据的装置和方法,该装置和方法可通过计算功率来最小化功耗 在输入原始数据或反相数据被写入PRAM并存储消耗较少功率的数据时消耗。 由于需要大电流长时间流动,所以PRAM消耗大量的功率以便将数据存储在存储单元中。 根据本发明,由于在写入值为0的数据和值为1的数据时,PRAM消耗不同的功率量,所以当输入原始数据被存储时消耗的功率和当输入的原始数据被反相时消耗的功率 并将其进行存储,将数据作为字单元写入PRAM时,存储具有较小功耗的数据,从而能够降低PRAM的功耗。

    Programmable logic block of FPGA using phase-change memory device
    10.
    发明授权
    Programmable logic block of FPGA using phase-change memory device 有权
    使用相变存储器件的FPGA的可编程逻辑块

    公开(公告)号:US07911227B2

    公开(公告)日:2011-03-22

    申请号:US12633731

    申请日:2009-12-08

    IPC分类号: G06F7/38 H03K19/173

    摘要: Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.

    摘要翻译: 提供了现场可编程门阵列(FPGA)的可编程逻辑块。 可编程逻辑块包括连接到电源的上拉访问晶体管,连接到上拉存取晶体管的上变相存储器件,连接到上变相存储晶体管的下变相存储器件 存储器件,上变相存储器件和下变相存储器件之间的输出端子以及连接到下变相存储器件和地的下拉存取晶体管。 上变相存储器件和下变相存储器件的电阻值被单独编程。