公开(公告)号：US20120292625A1

公开(公告)日：2012-11-22

申请号：US13475622

申请日：2012-05-18

申请人： Youngsuk SONG ,  Seungjin CHOI ,  Seongyeol YOO

发明人： Youngsuk SONG ,  Seungjin CHOI ,  Seongyeol YOO

IPC分类号： H01L33/16 ,  H01L33/60

CPC分类号： G02F1/1362 ,  G02F1/133555 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2201/48 ,  H01L27/1288

摘要： An embodiment of the disclosed technology provides a method of manufacturing an array substrate, comprising: a first mask process of forming an inorganic material protrusion on a base substrate; a second mask process of forming a reflective region pattern, a gate line, a gate electrode branched from the gate line, and a common electrode; a third mask process of forming an active island and a data line formed and forming a source electrode connected to the data line and a drain electrode on the active island and a channel; a fourth mask process of forming an insulation material layer, treating the insulation material layer to form a planarization layer, and forming a through hole above the drain electrode; and a fifth mask process of forming a pixel electrode and connected to the drain electrode via the through hole in a reflective region.

摘要翻译： 所公开的技术的一个实施例提供一种制造阵列基板的方法，包括：在基底基板上形成无机材料突起的第一掩模工艺; 形成反射区域图案的第二掩模工艺，栅极线，从栅极线分支的栅电极和公共电极; 形成有源岛和数据线的第三掩模处理，并且形成连接到有源岛上的数据线和漏电极的源电极和沟道; 形成绝缘材料层的第四掩模工艺，处理绝缘材料层以形成平坦化层，以及在漏电极之上形成通孔; 以及形成像素电极并通过反射区域中的通孔连接到漏电极的第五掩模处理。

公开(公告)号：US20120094472A1

公开(公告)日：2012-04-19

申请号：US13248908

申请日：2011-09-29

申请人： Seongyeol YOO ,  Youngsuk SONG ,  Seungjin CHOI ,  Zhanfeng CAO

发明人： Seongyeol YOO ,  Youngsuk SONG ,  Seungjin CHOI ,  Zhanfeng CAO

IPC分类号： H01L21/20

CPC分类号： G03F7/0035 ,  H01L27/124 ,  H01L27/1288

摘要： A method for fabricating a thin film pattern and a method for fabricating an array substrate are provided. The method for fabricating a thin film pattern comprises: forming a first film and a second film sequentially; applying a layer of photoresist on the second film; forming a photoresist pattern comprising a totally left region, a partially left region and a totally removed region; performing a first wet etching on the second film in the totally removed region; performing a first dry etching on the first film in the totally removed region to form a first pattern, and etching the photoresist layer to remove the photoresist in the partially left region to expose the second film in the partially left region; performing a second wet etching on the second film in the partially left region; performing a second dry etching to form a second pattern; and removing the residual photoresist.

摘要翻译： 提供一种薄膜图案的制造方法和阵列基板的制造方法。 制造薄膜图案的方法包括：依次形成第一膜和第二膜; 在第二膜上施加一层光致抗蚀剂; 形成包括完全左区域，部分左区域和完全去除区域的光致抗蚀剂图案; 在完全去除的区域中对第二膜执行第一湿蚀刻; 在完全去除的区域中对第一膜执行第一干蚀刻以形成第一图案，并蚀刻光致抗蚀剂层以去除部分左侧区域中的光致抗蚀剂，以暴露部分左侧区域中的第二膜; 在部分左侧区域中的第二膜上进行第二湿蚀刻; 执行第二干蚀刻以形成第二图案; 并除去残留的光致抗蚀剂。

公开(公告)号：US20100075451A1

公开(公告)日：2010-03-25

申请号：US12561344

申请日：2009-09-17

申请人： Seongyeol YOO ,  Youngsuk SONG ,  Seungjin CHOI

发明人： Seongyeol YOO ,  Youngsuk SONG ,  Seungjin CHOI

IPC分类号： H01L21/28 ,  H01L21/306

CPC分类号： H01L29/78603 ,  H01L27/1218 ,  H01L29/66765

摘要： The present invention discloses a method for manufacturing thin film structure, which comprises the following steps: providing a substrate having a first recess and a second recess formed therein with the first recess being deeper than the second recess; depositing a first material layer and a second material layer of different thicknesses successively on the substrate; and grinding the substrate so that a flat upper surface is formed and the first material layer and the second material layer are remained in the first recess while only the first material layer is remained in the second recess. The present invention also discloses a method for manufacturing fringe field switching type liquid crystal display array substrate. With the present invention, it is possible to make the upper surface flat while forming patterns on two layers of thin films respectively by using a single mask.

摘要翻译： 本发明公开了一种制造薄膜结构的方法，包括以下步骤：提供具有第一凹部和形成在其中的第二凹部的基板，其中第一凹部比第二凹部更深; 在衬底上依次沉积不同厚度的第一材料层和第二材料层; 并且研磨所述基板，使得形成平坦的上表面，并且所述第一材料层和所述第二材料层保留在所述第一凹部中，同时仅所述第一材料层保留在所述第二凹部中。 本发明还公开了一种用于制造条纹场开关型液晶显示阵列基板的方法。 利用本发明，可以通过使用单个掩模分别在两层薄膜上形成图案而使上表面平坦。

公开(公告)号：US20110013130A1

公开(公告)日：2011-01-20

申请号：US12836028

申请日：2010-07-14

申请人： Seungjin CHOI ,  Youngsuk SONG ,  Seongyeol YOO

发明人： Seungjin CHOI ,  Youngsuk SONG ,  Seongyeol YOO

IPC分类号： G02F1/1343 ,  H01L21/336

CPC分类号： H01L27/1288 ,  G02F1/134363 ,  G02F2001/134372 ,  H01L27/1214

摘要： A manufacturing method for an FFS type TFT-LCD array substrate comprises: depositing a first metal film on a transparent substrate, and form a gate line, a gate electrode and a common electrode line by a first patterning process; depositing a gate insulating layer, an active layer film and a second metal film sequentially and patterning the second metal film and the active layer film by a second patterning process; Step 3 depositing a first transparent conductive film and patterning the first transparent conductive film, the second metal film and the active layer film by a third patterning process; depositing a passivation layer, forming a connection hole by patterning the passivation layer through the fourth patterning process, performing an ashing process on photoresist used in the fourth patterning process, depositing a second transparent conductive layer on the remaining photoresist, and forming a common electrode by a lifting-off process.

摘要翻译： 一种FFS型TFT-LCD阵列基板的制造方法，其特征在于，在第一图案形成工序中，在透明基板上淀积第一金属膜，形成栅极线，栅电极，公共电极线; 依次沉积栅极绝缘层，有源层膜和第二金属膜，并通过第二图案化工艺图案化第二金属膜和有源层膜; 步骤3沉积第一透明导电膜并通过第三图案化工艺图案化第一透明导电膜，第二金属膜和有源层膜; 沉积钝化层，通过第四图案化工艺图案化钝化层形成连接孔，在第四图案化工艺中使用的光致抗蚀剂上进行灰化处理，在剩余光致抗蚀剂上沉积第二透明导电层，并通过 起吊过程。

公开(公告)号：US20120119232A1

公开(公告)日：2012-05-17

申请号：US13278360

申请日：2011-10-21

申请人： Youngsuk SONG ,  Seungjin CHOI ,  Seongyeol YOO

发明人： Youngsuk SONG ,  Seungjin CHOI ,  Seongyeol YOO

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  G02F2001/136236

摘要： An embodiment of the invention provides a method for manufacturing an array substrate, wherein the procedure for forming a data line, an active layer with a channel, a source electrode, a drain electrode and a pixel electrode comprises applying a photoresist on a data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern including a third thickness region, a second thickness region and a first thickness region whose thicknesses are successively increased, the third thickness region at least corresponding to the pixel electrode, the second thickness region corresponding to the data line, the active layer, the source electrode and the drain electrode, and the first thickness region corresponding to the other regions.

摘要翻译： 本发明的一个实施例提供了一种用于制造阵列基板的方法，其中用于形成数据线的步骤，具有沟道的有源层，源电极，漏电极和像素电极包括在数据线金属 薄膜，并通过使用多色调掩模进行曝光和显影处理，以形成包括第三厚度区域，第二厚度区域和厚度依次增加的第一厚度区域的光致抗蚀剂图案，第三厚度区域至少相应地 对应于数据线，有源层，源电极和漏电极的第二厚度区域和对应于其它区域的第一厚度区域到像素电极。

公开(公告)号：US20100295049A1

公开(公告)日：2010-11-25

申请号：US12784759

申请日：2010-05-21

申请人： Seongyeol YOO ,  Seungjin CHOI ,  Youngsuk SONG

发明人： Seongyeol YOO ,  Seungjin CHOI ,  Youngsuk SONG

IPC分类号： H01L33/08 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： The embodiment of the invention provides a manufacturing method for a thin film transistor liquid crystal display (TFT-LCD) array substrate, the manufacturing method comprises: step 1, depositing a transparent conductive film, a source/drain metal film and a doped semiconductor film on a transparent substrate sequentially, forming patterns of a doped semiconductor layer, a source electrode and a drain electrode of a thin film transistor, a data line and a pixel electrode by a first patterning process, wherein the doped semiconductor layer remains on the source electrode and the drain electrode; Step 2, depositing a semiconductor film on the whole transparent substrate after Step 1, forming a pattern of a semiconductor layer which includes a channel of the thin film transistor by a second patterning process; Step 3, depositing an insulating film and a gate metal film on the whole transparent substrate after Step 2, forming patterns of a gate line and a gate electrode of the thin film transistor by a third patterning process, wherein the gate electrode is located above the channel of the thin film transistor.

摘要翻译： 本发明的实施例提供一种薄膜晶体管液晶显示（TFT-LCD）阵列基板的制造方法，其制造方法包括：步骤1，沉积透明导电膜，源/漏金属膜和掺杂半导体膜 在透明基板上顺序地通过第一图案化工艺形成薄膜晶体管，数据线和像素电极的掺杂半导体层，源电极和漏电极的图案，其中掺杂半导体层保留在源极上 和漏电极; 步骤2，在步骤1之后，在整个透明衬底上沉积半导体膜，通过第二图案化工艺形成包括薄膜晶体管的沟道的半导体层的图案; 步骤3，在步骤2之后，在整个透明基板上沉积绝缘膜和栅极金属膜，通过第三图案化工艺形成薄膜晶体管的栅极线和栅电极的图案，其中栅电极位于 通道的薄膜晶体管。

公开(公告)号：US20100230682A1

公开(公告)日：2010-09-16

申请号：US12724047

申请日：2010-03-15

申请人： Youngsuk SONG ,  Seungjin CHOI ,  Seongyeol YOO

发明人： Youngsuk SONG ,  Seungjin CHOI ,  Seongyeol YOO

IPC分类号： H01L33/08 ,  H01L21/28

CPC分类号： H01L27/127 ,  H01L27/1248 ,  H01L27/1288

摘要： The present invention provides an array substrate comprising: a substrate, having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode and a drain electrode; a first metal layer, formed on the substrate, and comprising a gate line and the gate electrode of the TFT; a first insulating layer, covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer; a second insulating layer, covering the semiconductor layer, the ohmic contact layer, and the second metal layer; a pixel electrode, provided on the second insulating layer and is connected to the drain electrode. The second metal layer further comprises an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer.

摘要翻译： 本发明提供了一种阵列基板，包括：具有形成在其上的薄膜晶体管（TFT）的基板，所述TFT具有栅电极，源电极和漏电极; 第一金属层，形成在所述基板上，并且包括所述TFT的栅极线和所述栅电极; 覆盖所述第一金属层和所述基板的第一绝缘层; 半导体层，欧姆接触层和第二金属层，其顺序地形成在所述第一绝缘层上; 覆盖半导体层，欧姆接触层和第二金属层的第二绝缘层; 像素电极，设置在第二绝缘层上并连接到漏电极。 第二金属层还包括在像素电极和第一金属层之间的重叠区域内的像素电极的周边区域中的蚀刻阻挡图案。

公开(公告)号：US20090251646A1

公开(公告)日：2009-10-08

申请号：US12277487

申请日：2008-11-25

申请人： Seongyeol YOO

发明人： Seongyeol YOO

IPC分类号： G02F1/1335 ,  G03F7/20

CPC分类号： G02F1/133555 ,  G02F1/13439 ,  G02F2203/03 ,  H01L27/1214 ,  H01L27/1288

摘要： An embodiment of the invention provides an array substrate for a liquid crystal display comprising a substrate and a gate scanning line, a thin film transistor, a data line, and a passivation layer on the substrate, the passivation layer covering the gate scanning line, the thin film transistor, the data line, and a through hole being formed in the passivation layer. A pixel electrode is formed on the passivation layer and comprises a transmissive part and a reflective part, the transmissive part comprises an amorphous-type indium tin oxide film and a poly-type indium tin oxide film below the amorphous-type indium tin oxide film, and the reflective part comprises the poly-type indium tin oxide film and a metal film covering the poly-type indium tin oxide film.

摘要翻译： 本发明的一个实施例提供一种用于液晶显示器的阵列基板，其包括基板和栅极扫描线，薄膜晶体管，数据线和钝化层，所述钝化层覆盖所述栅极扫描线， 薄膜晶体管，数据线，以及形成在钝化层中的通孔。 像素电极形成在钝化层上，并且包括透射部分和反射部分，透射部分包括非晶型铟锡氧化物膜和位于非晶型铟锡氧化物膜下方的多型铟锡氧化物膜， 并且反射部分包括聚氧化铟锡氧化物膜和覆盖多晶型氧化铟锡膜的金属膜。

公开(公告)号：US20110297929A1

公开(公告)日：2011-12-08

申请号：US13150389

申请日：2011-06-01

申请人： Xiang LIU ,  Seongyeol YOO ,  Jianshe XUE

发明人： Xiang LIU ,  Seongyeol YOO ,  Jianshe XUE

IPC分类号： H01L33/16 ,  H01L29/24

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides an array substrate, comprising: a base substrate; a pixel electrode pattern and a gate pattern formed on the base substrate, the gate pattern comprises a gate scanning line and a gate electrode of a transistor, both of the gate scanning line and the gate electrode comprise transparent conductive metal layer and the gate metal layer stacking on the substrate, each pixel electrode in the pixel electrode pattern comprises transparent conductive metal layer; a gate insulating layer on the pixel electrode pattern and the gate pattern, an active layer pattern on the gate insulating layer and corresponding to the gate electrode, a via hole in the gate insulating layer for exposing the pixel electrode; and a source/drain pattern on the gate insulating layer, the source/drain pattern comprises a data scanning line crossing with the gate scanning line, source and drain electrodes of the transistor, and the drain electrode is in contact with the pixel electrode through the via hole.

摘要翻译： 本发明提供了一种阵列基板，包括：基底; 像素电极图案和形成在基底基板上的栅极图案，栅极图案包括栅极扫描线和晶体管的栅电极，栅极扫描线和栅电极都包括透明导电金属层和栅极金属层 在基板上堆叠，像素电极图案中的每个像素电极包括透明导电金属层; 像素电极图案和栅极图案上的栅极绝缘层，栅极绝缘层上的对应于栅电极的有源层图案，用于使像素电极露出的栅极绝缘层中的通孔; 以及栅极绝缘层上的源极/漏极图案，源极/漏极图案包括与栅极扫描线交叉的数据扫描线，晶体管的源极和漏极，并且漏极与像素电极通过 通孔。

公开(公告)号：US20120276697A1

公开(公告)日：2012-11-01

申请号：US13458478

申请日：2012-04-27

申请人： Zhanfeng CAO ,  Seongyeol YOO ,  Qi YAO

发明人： Zhanfeng CAO ,  Seongyeol YOO ,  Qi YAO

IPC分类号： H01L21/336

CPC分类号： H01L27/1288

摘要： A manufacturing method of an array substrate, comprising the following steps: S1 forming a gate signal line and a gate electrode on a base substrate, successively depositing a gate insulating layer, an active layer, and a metal layer, faulting a mask formed of photoresist on the metal layer, and removing the metal layer outside a region for forming a data line and source/drain electrodes through the mask; S2. simultaneously etching the active layer and ashing the photoresist so as to expose the metal layer within a channel region; S3. etching the active layer exposed by the photoresist after being ashed after the step S2; S4. removing the metal layer within the channel region.

摘要翻译： 一种阵列基板的制造方法，包括以下步骤：在基底基板上形成栅极信号线和栅电极，依次沉积栅极绝缘层，有源层和金属层，使由光致抗蚀剂形成的掩模 在金属层上，并且通过掩模除去用于形成数据线和源/漏电极的区域之外的金属层; S2。 同时蚀刻有源层并使光致抗蚀剂灰化，以使沟道区域内的金属层露出; S3。 在步骤S2之后，在灰化后蚀刻由光刻胶曝光的活性层; S4。 去除沟道区域内的金属层。