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公开(公告)号：US20100302837A1
公开(公告)日：2010-12-02
申请号：US12474078
申请日：2009-05-28
CPC分类号： G11C11/413 , G11C7/106 , G11C7/12
摘要： A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.
摘要翻译： 存储器具有第一位线，第二位线和字线。 存储单元耦合到字线和第一和第二位线。 读出放大器具有第一输入，第二输入，第一输出和第二输出。 一对耦合晶体管包括第一晶体管和第二晶体管。 在一个实施例中，第一晶体管耦合在第一位线和读出放大器的第一输入端之间，第二晶体管耦合在第二位线和读出放大器的第二输入端之间。 写回电路耦合到读出放大器的输出端。 写回电路在读周期期间将从存储单元读取的值写回到存储器单元。
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公开(公告)号：US08009489B2
公开(公告)日：2011-08-30
申请号：US12474078
申请日：2009-05-28
CPC分类号： G11C11/413 , G11C7/106 , G11C7/12
摘要： A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.
摘要翻译： 存储器具有第一位线，第二位线和字线。 存储单元耦合到字线和第一和第二位线。 读出放大器具有第一输入，第二输入，第一输出和第二输出。 一对耦合晶体管包括第一晶体管和第二晶体管。 在一个实施例中，第一晶体管耦合在第一位线和读出放大器的第一输入端之间，第二晶体管耦合在第二位线和读出放大器的第二输入端之间。 写回电路耦合到读出放大器的输出端。 写回电路在读周期期间将从存储单元读取的值写回到存储器单元。
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公开(公告)号：US20100246298A1
公开(公告)日：2010-09-30
申请号：US12414761
申请日：2009-03-31
CPC分类号： G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/50
摘要： A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.
摘要翻译： 提供了一种用于访问存储器的存储器和方法。 第一个测试用于测试存储器元件以确定最低电源电压，在该最低电源电压下，所有存储器元件将在该最低电源电压下操作以确定弱存储器元件。 冗余用于替代冗余存储器元件作为弱存储元件。 弱记忆元素被指定为测试元素。 响应于接收到更改提供给存储器元件的电源电压的请求，使用第二测试来测试测试元件以确定测试元件是否将在新的电源电压下正常工作。 如果测试元件通过第二次测试，则以新的电源电压访问存储器元件。 如果测试元件在第二次测试中失败，则使用访问辅助操作访问存储器元件。
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公开(公告)号：US08315117B2
公开(公告)日：2012-11-20
申请号：US12414761
申请日：2009-03-31
IPC分类号： G11C29/00
CPC分类号： G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/24 , G11C29/50
摘要： A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.
摘要翻译： 提供了一种用于访问存储器的存储器和方法。 第一个测试用于测试存储器元件以确定最低电源电压，在该最低电源电压下，所有存储器元件将在该最低电源电压下操作以确定弱存储器元件。 冗余用于替代冗余存储器元件作为弱存储元件。 弱记忆元素被指定为测试元素。 响应于接收到更改提供给存储器元件的电源电压的请求，使用第二测试来测试测试元件以确定测试元件是否将在新的电源电压下正常工作。 如果测试元件通过第二次测试，则以新的电源电压访问存储器元件。 如果测试元件在第二次测试中失败，则使用访问辅助操作访问存储器元件。
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公开(公告)号：US08004907B2
公开(公告)日：2011-08-23
申请号：US12479088
申请日：2009-06-05
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.
摘要翻译： 存储器包括包括一对交叉耦合的反相器的SRAM位单元，其中该对的第一反相器包括具有本体的第一器件和该对的第二反相器，其包括具有主体的第二器件。 第一选择电路具有耦合到第一电源电压端子的第一输入端，耦合到第二电源电压端子的第二输入端和耦合到第一器件的第一电流电极和第二器件的第一电流电极的输出端 。 第二选择电路具有耦合到第一电源电压端子的第一输入端，耦合到第二电源电压端子的第二输入端和耦合到第一和第二设备中的每一个的主体的输出端。 耦合到SRAM位单元的字线由耦合到第一电源电压端子的字线驱动器驱动。
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公开(公告)号：US20100191990A1
公开(公告)日：2010-07-29
申请号：US12360656
申请日：2009-01-27
申请人： Shayan Zhang , James D. Burnett , Prashant U. Kenkare , Hema Ramamurthy , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Prashant U. Kenkare , Hema Ramamurthy , Andrew C. Russell , Michael D. Snyder
CPC分类号： G06F12/0864 , G06F2212/1028 , G11C7/04 , G11C2207/2245 , Y02D10/13
摘要： A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.
摘要翻译： 当存储器的电源电压降低以降低功率和/或增加耐久性时，存储器就会失败。 当电源电压升高到原始值时，这些位变得正常工作。 随着电压降低，不使用包含非功能位的存储器部分。 许多内存可能保持功能，并保留使用。 当电压增加时，因为由于电源电压降低而不被使用的存储器部分可以被再次使用。 这在缓存中特别有用，其中由于电源电压降低引起的可用存储器的减少可以被实现为方式数量的减少。 因此，例如，当功率降低或耐力增加时，八路缓存可以简单地简化为四路高速缓存。
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公开(公告)号：US08059482B2
公开(公告)日：2011-11-15
申请号：US12487791
申请日：2009-06-19
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/145
摘要： A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage.
摘要翻译： 存储器具有操作的方法，包括执行第一类型和第二类型的操作。 在第一类型的第一操作期间，第一电压耦合到存储器阵列的第一存储器单元的电源节点。 响应于终止第一类型的第一操作，第一电压与电源节点解耦，以允许电源节点漂移。 如果电源节点漂移到第二电压，则电源被耦合到电源节点。 这有助于降低产生第一电压的电路中的功率。
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公开(公告)号：US20100309736A1
公开(公告)日：2010-12-09
申请号：US12479088
申请日：2009-06-05
CPC分类号： G11C11/413
摘要： A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.
摘要翻译： 存储器包括包括一对交叉耦合的反相器的SRAM位单元，其中该对的第一反相器包括具有本体的第一器件和该对的第二反相器，其包括具有主体的第二器件。 第一选择电路具有耦合到第一电源电压端子的第一输入端，耦合到第二电源电压端子的第二输入端和耦合到第一器件的第一电流电极和第二器件的第一电流电极的输出端 。 第二选择电路具有耦合到第一电源电压端子的第一输入端，耦合到第二电源电压端子的第二输入端和耦合到第一和第二设备中的每一个的主体的输出端。 耦合到SRAM位单元的字线由耦合到第一电源电压端子的字线驱动器驱动。
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9.发明申请INTEGRATED CIRCUIT HAVING MEMORY REPAIR INFORMATION STORAGE AND METHOD THEREFOR 有权具有记忆修复信息的集成电路存储及其方法公开(公告)号：US20100277990A1
公开(公告)日：2010-11-04
申请号：US12433330
申请日：2009-04-30
CPC分类号： G11C5/147 , G11C7/1045 , G11C8/08 , G11C11/4074 , G11C29/028 , G11C29/50 , G11C29/802 , G11C2029/4402 , G11C2229/726
摘要： A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to an operating condition of the circuit changing to the selected operating condition. This allows for efficiently identifying the few circuits that do not meet specified requirements based on a reduction in, for example, operating voltage, and altering their operation in order to meet the specified requirements relative to the reduced operating voltage without having to do so for the vast majority of the circuits that are able to meet the requirements at the lowered operating voltage.
摘要翻译： 集成电路上的存储单元存储识别集成电路上的电路，所选择的操作条件以及用于所选择的操作条件的电路的所需操作配置的信息。 响应于电路的操作条件改变到所选择的操作条件，操作电路的方式被改变为所需的操作配置。 这允许基于例如工作电压的降低以及改变其操作来有效地识别不符合规定要求的几个电路，以便相对于降低的工作电压来满足规定的要求，而不需要这样做 绝大多数电路能够在降低的工作电压下满足要求。
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10.发明授权公开(公告)号：US07292495B1
公开(公告)日：2007-11-06
申请号：US11427610
申请日：2006-06-29
申请人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
发明人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/419
摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
摘要翻译： 提供具有低电压读/写操作的集成电路。 集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列 的存储器单元包括位线和耦合到位线的所有存储器单元。 集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电 多个存储单元的第一访问操作。 集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电 的记忆细胞。
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