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1.发明授权Clocked memory with word line activation during a first portion of the clock cycle 有权在时钟周期的第一部分，具有字线激活的时钟存储器公开(公告)号：US08743651B2
公开(公告)日：2014-06-03
申请号：US13491722
申请日：2012-06-08
摘要： A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.
摘要翻译： 存储器包括多个锁存预解码器，每个锁存预解码器包括耦合在电源电压和锁存器之间并且具有耦合到时钟信号的控制电极的第一晶体管; 耦合到所述第一晶体管并且具有耦合到第一地址位信号的控制电极的第二晶体管; 耦合到第二晶体管并具有耦合到第二地址位信号的控制电极的第三晶体管; 第四晶体管，耦合到第三晶体管，并具有耦合到时钟信号的延迟和反相形式的控制电极; 耦合在所述第四晶体管和地之间并具有耦合到所述时钟信号的控制电极的第五晶体管; 以及在时钟周期的第二部分期间在时钟信号的时钟周期的第一部分和预定逻辑电平期间提供预解码值的输出。
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2.发明申请公开(公告)号：US20140036610A1
公开(公告)日：2014-02-06
申请号：US13563224
申请日：2012-07-31
申请人： HEMA RAMAMURTHY
发明人： HEMA RAMAMURTHY
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048 , G11C11/419
摘要： A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle.
摘要翻译： 具有存储器阵列的存储器，其具有耦合到位线的位单元。 存储器还包括预充电位线的预充电电路。 存储器还包括耦合到预充电电路的控制电路，其使读取周期的开始部分处的预充电电路能够将预充电电路保持为禁止，直到读周期结束，并且在写周期期间使预充电电路保持禁止。 一种操作存储器的方法，其中存储器包括耦合到位线的存储器单元的阵列，包括在读周期的开始处对位线进行预充电。 该方法还包括在写周期的持续时间内阻止位线的预充电。
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公开(公告)号：US08156357B2
公开(公告)日：2012-04-10
申请号：US12360656
申请日：2009-01-27
申请人： Shayan Zhang , James D. Burnett , Prashant U. Kenkare , Hema Ramamurthy , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Prashant U. Kenkare , Hema Ramamurthy , Andrew C. Russell , Michael D. Snyder
IPC分类号： G06F1/32
CPC分类号： G06F12/0864 , G06F2212/1028 , G11C7/04 , G11C2207/2245 , Y02D10/13
摘要： A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.
摘要翻译： 当存储器的电源电压降低以降低功率和/或增加耐久性时，存储器就会失败。 当电源电压升高到原始值时，这些位变得正常工作。 随着电压降低，不使用包含非功能位的存储器部分。 许多内存可能保持功能，并保留使用。 当电压增加时，因为由于电源电压降低而不被使用的存储器部分可以被再次使用。 这在缓存中特别有用，其中由于电源电压降低引起的可用存储器的减少可以被实现为方式数量的减少。 因此，例如，当功率降低或耐力增加时，八路缓存可以简单地简化为四路高速缓存。
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4.发明授权公开(公告)号：US08817562B2
公开(公告)日：2014-08-26
申请号：US13563224
申请日：2012-07-31
申请人： Hema Ramamurthy
发明人： Hema Ramamurthy
CPC分类号： G11C7/12 , G11C7/1048 , G11C11/419
摘要： A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle.
摘要翻译： 具有存储器阵列的存储器，其具有耦合到位线的位单元。 存储器还包括预充电位线的预充电电路。 存储器还包括耦合到预充电电路的控制电路，其使读取周期的开始部分处的预充电电路能够将预充电电路保持为禁止，直到读周期结束，并且在写周期期间使预充电电路保持禁止。 一种操作存储器的方法，其中存储器包括耦合到位线的存储器单元的阵列，包括在读周期的开始处对位线进行预充电。 该方法还包括在写周期的持续时间内阻止位线的预充电。
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公开(公告)号：US20100191990A1
公开(公告)日：2010-07-29
申请号：US12360656
申请日：2009-01-27
申请人： Shayan Zhang , James D. Burnett , Prashant U. Kenkare , Hema Ramamurthy , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Prashant U. Kenkare , Hema Ramamurthy , Andrew C. Russell , Michael D. Snyder
CPC分类号： G06F12/0864 , G06F2212/1028 , G11C7/04 , G11C2207/2245 , Y02D10/13
摘要： A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.
摘要翻译： 当存储器的电源电压降低以降低功率和/或增加耐久性时，存储器就会失败。 当电源电压升高到原始值时，这些位变得正常工作。 随着电压降低，不使用包含非功能位的存储器部分。 许多内存可能保持功能，并保留使用。 当电压增加时，因为由于电源电压降低而不被使用的存储器部分可以被再次使用。 这在缓存中特别有用，其中由于电源电压降低引起的可用存储器的减少可以被实现为方式数量的减少。 因此，例如，当功率降低或耐力增加时，八路缓存可以简单地简化为四路高速缓存。
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公开(公告)号：US08861301B2
公开(公告)日：2014-10-14
申请号：US13491712
申请日：2012-06-08
摘要： A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.
摘要翻译： 存储器包括具有多个字线的存储器阵列，多个锁存预解码器和字线驱动器逻辑。 每个锁存预解码器响应于时钟信号的时钟周期的第一个边缘，接收时钟信号和多个地址信号并锁存多个地址信号的逻辑功能的结果，并响应于 时钟信号的第一时钟周期的第二边缘，其中响应于第二边缘，多个锁存预解码器中的每个锁存解码器提供相同的预定值。 字线驱动器逻辑响应于锁存结果选择性地激活多个字线中的选定字线。
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公开(公告)号：US20130329511A1
公开(公告)日：2013-12-12
申请号：US13491712
申请日：2012-06-08
IPC分类号： G11C8/10
摘要： A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.
摘要翻译： 存储器包括具有多个字线的存储器阵列，多个锁存预解码器和字线驱动器逻辑。 每个锁存预解码器响应于时钟信号的时钟周期的第一个边缘，接收时钟信号和多个地址信号并锁存多个地址信号的逻辑功能的结果，并响应于 时钟信号的第一时钟周期的第二边缘，其中响应于第二边缘，多个锁存预解码器中的每个锁存解码器提供相同的预定值。 字线驱动器逻辑响应于锁存结果选择性地激活多个字线中的选定字线。
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8.发明申请INTEGRATED CIRCUIT MEMORY HAVING DYNAMICALLY ADJUSTABLE READ MARGIN AND METHOD THEREFOR 有权具有动态可调整性的集成电路存储器及其方法公开(公告)号：US20090103379A1
公开(公告)日：2009-04-23
申请号：US11875997
申请日：2007-10-22
申请人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
发明人： Shayan Zhang , Hema Ramamurthy , Zheng Xu , Michael D. Snyder
CPC分类号： G11C29/02 , G11C11/41 , G11C29/026 , G11C29/028 , G11C2029/0409
摘要： A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.
摘要翻译： 提供了一种用于在包括多个可寻址单元的集成电路中在操作期间动态地控制存储器的读出放大器差分裕度的方法。 该方法包括将与多个可寻址单元相对应的读出放大器差分裕度设置为第一值。 该方法还包括如果当从多个可寻址单元的集合读取数据时发生读取数据错误，则将与多个可寻址单元相对应的读出放大器差分裕度设置为第二值，其中第二值大于 第一个值。
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9.发明授权
公开(公告)号：US5483170A
公开(公告)日：1996-01-09
申请号：US110868
申请日：1993-08-24
CPC分类号： G01R31/3004
摘要： A method and apparatus for detecting faults in digital, analog, and hybrid integrated circuits is disclosed. A single test vector employing bias voltage on input used in conjunction with pulsing the power supply rails is used to allow detection of the various faults which may be present. The instantaneous rail current (i.sub.DD) is then employed for analysis of the circuit, preferably by neural network.
摘要翻译： 公开了一种用于检测数字，模拟和混合集成电路中的故障的方法和装置。 使用与脉冲电源轨一起使用的输入上使用偏置电压的单个测试矢量来允许检测可能存在的各种故障。 然后，优选通过神经网络将瞬时轨道电流（iDD）用于电路的分析。
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10.发明申请CLOCKED MEMORY WITH WORD LINE ACTIVATION DURING A FIRST PORTION OF THE CLOCK CYCLE 有权在时钟周期的第一部分中使用字线激活的时钟记忆公开(公告)号：US20130329512A1
公开(公告)日：2013-12-12
申请号：US13491722
申请日：2012-06-08
IPC分类号： G11C8/10
摘要： A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.
摘要翻译： 存储器包括多个锁存预解码器，每个锁存预解码器包括耦合在电源电压和锁存器之间并且具有耦合到时钟信号的控制电极的第一晶体管; 耦合到所述第一晶体管并且具有耦合到第一地址位信号的控制电极的第二晶体管; 耦合到第二晶体管并具有耦合到第二地址位信号的控制电极的第三晶体管; 第四晶体管，耦合到第三晶体管，并具有耦合到时钟信号的延迟和反相形式的控制电极; 耦合在所述第四晶体管和地之间并具有耦合到所述时钟信号的控制电极的第五晶体管; 以及在时钟周期的第二部分期间在时钟信号的时钟周期的第一部分和预定逻辑电平期间提供预解码值的输出。
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