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公开(公告)号：US07453280B1
公开(公告)日：2008-11-18
申请号：US11896364
申请日：2007-08-31
申请人： Sheng-Hui Liang , Chia-Lin Chen , Pei-Chun Liao , Chin-Yuan Ko
发明人： Sheng-Hui Liang , Chia-Lin Chen , Pei-Chun Liao , Chin-Yuan Ko
CPC分类号： G01R31/2623 , G01R31/2831 , G01R31/2894 , G11C11/41 , G11C29/006 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , G11C2029/5006
摘要： A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.
摘要翻译： 提供了一种用于测试晶片级的一批半导体器件的方法。 该方法包括以下步骤：（a）获得每个半导体器件的栅极电介质的击穿电压; （b）向每个半导体器件的栅极电介质施加低于击穿电压但高于半导体器件的栅极电介质的基极电压的应力电压; （c）在步骤（b）之后，测量每个半导体器件在基极电压下的栅极电介质的电流; 和（d）从测量的电流获得拖尾分布。
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公开(公告)号：US07307880B2
公开(公告)日：2007-12-11
申请号：US11272657
申请日：2005-11-14
申请人： Chin-Yuan Ko , Yung-Sheng Tsai , Pei-Chun Liao
发明人： Chin-Yuan Ko , Yung-Sheng Tsai , Pei-Chun Liao
IPC分类号： G11C11/34
摘要： An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder.
摘要翻译： 提供一种化学镀设备。 化学镀设备包括晶片保持器; 在晶片保持器上方的化学分配喷嘴; 连接到化学分配喷嘴的导管; 以及在晶片保持器上方的辐射源。
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公开(公告)号：US20070109852A1
公开(公告)日：2007-05-17
申请号：US11272657
申请日：2005-11-14
申请人： Chin-Yuan Ko , Yung-Sheng Tsai , Pei-Chun Liao
发明人： Chin-Yuan Ko , Yung-Sheng Tsai , Pei-Chun Liao
IPC分类号： G11C16/04
摘要： A non-volatile memory cell based on a soft breakdown mechanism is provided. The memory cell comprises a resistor coupled serially to a gate or source/drain regions of a MOS device. When a soft breakdown occurs to the MOS device, leakage current flowing through the gate dielectric increases. The change of the leakage current is used to indicate different states.
摘要翻译： 提供了基于软击穿机构的非易失性存储单元。 存储单元包括串联连接到MOS器件的栅极或源极/漏极区域的电阻器。 当MOS器件发生软击穿时，流过栅极电介质的漏电流增加。 泄漏电流的变化用于表示不同的状态。
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公开(公告)号：US07579859B2
公开(公告)日：2009-08-25
申请号：US11763077
申请日：2007-06-14
申请人： Pei-Chun Liao , Chia-Lin Chen
发明人： Pei-Chun Liao , Chia-Lin Chen
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/129 , G01R31/2623
摘要： The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, the second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.
摘要翻译： 本发明提供一种由于时间依赖介电击穿（TDDB）确定半导体器件的寿命的方法。 该方法包括提供设置为MOS晶体管的栅介质层的介质层的多个样本，其近似源/漏电流密度分布作为施加在样本上的电压的第一函数，将基板电流密度分布近似为第二 作为施加在样品上的电压的函数，近似作为源/漏电流密度和样品中的衬底电流密度的第三函数的介电层寿命分布，从第一，第二和第三函数导出经验模型，其中 介电层寿命是施加在其上的电压的函数，并且使用该模型来确定在预定的工作栅极电压下的介电层寿命。
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公开(公告)号：US20080309365A1
公开(公告)日：2008-12-18
申请号：US11763077
申请日：2007-06-14
申请人： Pei-Chun Liao , Chia-Lin Chen
发明人： Pei-Chun Liao , Chia-Lin Chen
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/129 , G01R31/2623
摘要： The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.
摘要翻译： 本发明提供一种由于时间依赖介电击穿（TDDB）确定半导体器件的寿命的方法。 该方法包括提供设置为MOS晶体管的栅介质层的介质层的多个样本，其近似源/漏电流密度分布作为施加在样本上的电压的第一函数，将基板电流密度分布近似为第二 作为施加在样品上的电压的函数，近似作为源/漏电流密度和样品中的衬底电流密度的第三函数的介电层寿命分布，从第一，第二和第三函数导出经验模型，其中 介电层寿命是施加在其上的电压的函数，并且使用该模型来确定在预定的工作栅极电压下的介电层寿命。
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公开(公告)号：US08854561B2
公开(公告)日：2014-10-07
申请号：US12590765
申请日：2009-11-13
申请人： Pei-Chun Liao , Tien-Lun Ting , Wen-Hao Hsu , Hung-Lung Hou
发明人： Pei-Chun Liao , Tien-Lun Ting , Wen-Hao Hsu , Hung-Lung Hou
IPC分类号： G02F1/1343 , G02F1/136 , G09G3/36 , G02F1/1362 , G02F1/1337
CPC分类号： G09G3/3648 , G02F1/133707 , G02F1/136213 , G02F1/13624 , G09G3/3659 , G09G2300/0443 , G09G2300/0447 , G09G2300/0852 , G09G2310/0205 , G09G2310/0251 , G09G2320/028
摘要： A LCD panel in which a pixel has a first sub-pixel area and a second sub-pixel area, each area having a storage capacitor. Each pixel has a first gate line for providing a first gate-line signal for charging the first and second storage capacitors, and a second gate line for providing a second gate-line signal for removing part of the charges in the second storage capacitor to a third capacitor after the first gate-line signal has passed. The width of the first and second gate-line signals and their timing can be varied so that the first gate-line signal provided to a row can be used as the second gate-line signal to one of the preceding rows. In some embodiments, a pixel in each row has a duplicate pixel arranged to similarly receive the first and second gate-line signals, but data signals are received from different data lines.
摘要翻译： 一种像素具有第一子像素区域和第二子像素区域的LCD面板，每个区域都具有存储电容器。 每个像素具有用于提供用于对第一和第二存储电容器充电的第一栅极线信号的第一栅极线和用于提供第二栅极线信号的第二栅极线，用于将第二存储电容器中的部分电荷去除为 第三个电容器经过第一个栅极线信号。 可以改变第一和第二栅极线信号的宽度及其定时，使得提供给行的第一栅极线信号可以用作前一行之一的第二栅极线信号。 在一些实施例中，每行中的像素具有布置成类似地接收第一和第二栅极线信号的复制像素，但是从不同的数据线接收数据信号。
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公开(公告)号：US20090135321A1
公开(公告)日：2009-05-28
申请号：US12213252
申请日：2008-06-17
申请人： Ting-Wei Su , Pei-Chun Liao , Hung-Lung Hou
发明人： Ting-Wei Su , Pei-Chun Liao , Hung-Lung Hou
IPC分类号： G02F1/133 , G02F1/1343
CPC分类号： G02F1/134336 , G02F1/133707 , G02F1/13624 , G02F2001/134345 , G09G3/3614 , G09G3/3648 , G09G2300/0443 , G09G2320/0209
摘要： A pixel structure of liquid crystal display including a first and a second sub-pixel electrodes, a first and a second data lines, a gate line, and a first and a second transistors is provided. The first and the second sub-pixel electrodes disposed in the first and second sub-pixel areas respectively include at least two display domains at left and right. The first data line is disposed under the interface between two domains of each of the first and second sub-pixel electrodes, and the second data line is disposed under the edges of the first and second sub-pixel electrodes. The gate line is disposed between the first and second sub-pixel areas. The first sub-pixel electrode is controlled by the gate line and the first data line through the first transistor. The second sub-pixel electrode is controlled by the gate line and the second data line through the second transistor.
摘要翻译： 提供包括第一和第二子像素电极，第一和第二数据线，栅极线以及第一和第二晶体管的液晶显示器的像素结构。 设置在第一子像素区域和第二子像素区域中的第一子像素电极和第二子像素电极分别在左侧和右侧包括至少两个显示域。 第一数据线设置在第一和第二子像素电极中的每一个的两个畴之间的界面下方，并且第二数据线设置在第一和第二子像素电极的边缘下方。 栅极线设置在第一和第二子像素区域之间。 第一子像素电极由栅极线和第一数据线通过第一晶体管控制。 第二子像素电极由栅极线和第二数据线通过第二晶体管控制。
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公开(公告)号：US09158164B2
公开(公告)日：2015-10-13
申请号：US13301783
申请日：2011-11-22
申请人： Chin-An Tseng , Sheng-Ju Ho , Tien-Lun Ting , Cheng-Han Tsao , Ming-Yung Huang , Yen-Heng Huang , Pei-Chun Liao , Wen-Hao Hsu
发明人： Chin-An Tseng , Sheng-Ju Ho , Tien-Lun Ting , Cheng-Han Tsao , Ming-Yung Huang , Yen-Heng Huang , Pei-Chun Liao , Wen-Hao Hsu
IPC分类号： G02F1/1362 , G02F1/1343 , G02F1/1335 , G09G3/00 , G09G3/36 , G02B27/26
CPC分类号： G02F1/134336 , G02B27/26 , G02F1/133512 , G02F1/13624 , G02F2001/134345 , G09G3/003 , G09G3/3659 , G09G2300/0443 , G09G2300/0809
摘要： A pixel array substrate and a display panel are provided. The pixel array substrate includes a substrate, scan line groups, data lines, and pixel structures. The scan line groups are disposed on the substrate. The data lines are intersected with the scan line groups. The pixel structures are connected to the scan line groups and the data lines. Each pixel structure includes an active device group, a first pixel electrode, a second pixel electrode, and a connection electrode. The first pixel electrode is located between the second pixel electrode and the nth scan line group. The connection electrode is located at a side of the first pixel electrode adjacent to one data line. The second pixel electrode is electrically connected to the active device group through the connection electrode. The connection electrode, the first pixel electrode, and the second pixel electrode are of the same layer.
摘要翻译： 提供像素阵列基板和显示面板。 像素阵列基板包括基板，扫描线组，数据线和像素结构。 扫描线组设置在基板上。 数据线与扫描线组相交。 像素结构连接到扫描线组和数据线。 每个像素结构包括有源器件组，第一像素电极，第二像素电极和连接电极。 第一像素电极位于第二像素电极和第n扫描线组之间。 连接电极位于与一条数据线相邻的第一像素电极的一侧。 第二像素电极通过连接电极与有源器件组电连接。 连接电极，第一像素电极和第二像素电极具有相同的层。
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公开(公告)号：US08194021B2
公开(公告)日：2012-06-05
申请号：US12188577
申请日：2008-08-08
申请人： Pei-Chun Liao , Hung-Lung Hou
发明人： Pei-Chun Liao , Hung-Lung Hou
CPC分类号： G09G3/3659 , G09G3/3607 , G09G3/3614 , G09G2310/0205 , G09G2320/028
摘要： A display apparatus, pixel structure and drive method thereof are provided. The display apparatus comprises a gate drive chip, a first gate line, a second gate line, a first pixel unit, and a second pixel unit. The gate driver is configured to generate a first gate drive signal and a second gate drive signal. The first and second gate drive signals are outputted to the first and second gate lines, respectively. Furthermore, the first and second gate drive signals are configured to adjust a first feed through (FT) voltage generated by a first pixel area of the first pixel unit, a second FT voltage generated by a second pixel area of the first pixel unit, a third FT voltage generated by a third pixel area of the second pixel unit, and a fourth FT voltage generated by a fourth pixel area of the second pixel unit.
摘要翻译： 提供了一种显示装置，像素结构及其驱动方法。 显示装置包括栅极驱动芯片，第一栅极线，第二栅极线，第一像素单元和第二像素单元。 栅极驱动器被配置为产生第一栅极驱动信号和第二栅极驱动信号。 第一和第二栅极驱动信号分别输出到第一和第二栅极线。 此外，第一和第二栅极驱动信号被配置为调整由第一像素单元的第一像素区域产生的第一馈通（FT）电压，由第一像素单元的第二像素区域产生的第二FT电压， 由第二像素单元的第三像素区域产生的第三FT电压和由第二像素单元的第四像素区域产生的第四FT电压。
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公开(公告)号：US20090295695A1
公开(公告)日：2009-12-03
申请号：US12188577
申请日：2008-08-08
申请人： Pei-Chun Liao , Hung-Lung Hou
发明人： Pei-Chun Liao , Hung-Lung Hou
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G09G3/3607 , G09G3/3614 , G09G2310/0205 , G09G2320/028
摘要： A display apparatus, pixel structure and drive method thereof are provided. The display apparatus comprises a gate drive chip, a first gate line, a second gate line, a first pixel unit, and a second pixel unit. The gate driver is configured to generate a first gate drive signal and a second gate drive signal. The first and second gate drive signals are outputted to the first and second gate lines, respectively. Furthermore, the first and second gate drive signals are configured to adjust a first feed through (FT) voltage generated by a first pixel area of the first pixel unit, a second FT voltage generated by a second pixel area of the first pixel unit, a third FT voltage generated by a first pixel area of the second pixel unit, and a fourth FT voltage generated by a second pixel area of the second pixel unit.
摘要翻译： 提供了一种显示装置，像素结构及其驱动方法。 显示装置包括栅极驱动芯片，第一栅极线，第二栅极线，第一像素单元和第二像素单元。 栅极驱动器被配置为产生第一栅极驱动信号和第二栅极驱动信号。 第一和第二栅极驱动信号分别输出到第一和第二栅极线。 此外，第一和第二栅极驱动信号被配置为调整由第一像素单元的第一像素区域产生的第一馈通（FT）电压，由第一像素单元的第二像素区域产生的第二FT电压， 由第二像素单元的第一像素区域产生的第三FT电压和由第二像素单元的第二像素区域产生的第四FT电压。
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