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210 条记录 (耗时 0.026 秒)

    In-situ critical dimension measurement
    1.
    发明授权
    In-situ critical dimension measurement 有权
    原位临界尺寸测量

    公开(公告)号：US07301645B2

    公开(公告)日：2007-11-27

    申请号：US11053300

    申请日：2005-02-07

    申请人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

    发明人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

    IPC分类号： G01B11/02

    CPC分类号： H01L22/20

    摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.

    摘要翻译： 提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

    In-situ critical dimension measrument
    2.
    发明申请
    In-situ critical dimension measrument 有权
    原位关键维度测量

    公开(公告)号：US20060046323A1

    公开(公告)日：2006-03-02

    申请号：US11053300

    申请日：2005-02-07

    申请人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

    发明人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

    IPC分类号： H01L21/66

    CPC分类号： H01L22/20

    摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.

    摘要翻译： 提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

    ETCHING PROCESS TO AVOID POLYSILICON NOTCHING
    3.
    发明申请
    ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
    蚀刻过程避免多晶硅缺口

    公开(公告)号：US20060154487A1

    公开(公告)日：2006-07-13

    申请号：US11033912

    申请日：2005-01-11

    申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    IPC分类号： H01L21/8234 ,  H01L21/302

    CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

    摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

    摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

    Etching process to avoid polysilicon notching
    4.
    发明授权
    Etching process to avoid polysilicon notching 有权
    蚀刻工艺避免多晶硅切口

    公开(公告)号：US07109085B2

    公开(公告)日：2006-09-19

    申请号：US11033912

    申请日：2005-01-11

    申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

    摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

    摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

    Multilayer hard mask
    6.
    发明授权
    Multilayer hard mask 有权
    多层硬掩模

    公开(公告)号：US08372755B2

    公开(公告)日：2013-02-12

    申请号：US12686866

    申请日：2010-01-13

    申请人： Shiang-Bau Wang ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Hun-Jan Tao

    IPC分类号： H01L21/302 ,  H01L29/66

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有 厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

    Multilayer Hard Mask
    9.
    发明申请
    Multilayer Hard Mask 有权
    多层硬面膜

    公开(公告)号：US20110171804A1

    公开(公告)日：2011-07-14

    申请号：US12686866

    申请日：2010-01-13

    申请人： Shiang-Bau Wang ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有 厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

    Phosphoric acid free process for polysilicon gate definition
    10.
    发明授权
    Phosphoric acid free process for polysilicon gate definition 有权
    多晶硅栅极定义的无磷酸工艺

    公开(公告)号：US07307009B2

    公开(公告)日：2007-12-11

    申请号：US10999270

    申请日：2004-11-29

    申请人： Li-Te S. Lin ,  Fang-Cheng Chen ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    发明人： Li-Te S. Lin ,  Fang-Cheng Chen ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    IPC分类号： H01L21/00

    CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

    摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

    摘要翻译： 在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。 在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。 使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。 使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。