公开(公告)号：US07307009B2

公开(公告)日：2007-12-11

申请号：US10999270

申请日：2004-11-29

申请人： Li-Te S. Lin ,  Fang-Cheng Chen ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te S. Lin ,  Fang-Cheng Chen ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/00

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

摘要翻译： 在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。 在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。 使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。 使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

公开(公告)号：US06849531B1

公开(公告)日：2005-02-01

申请号：US10718876

申请日：2003-11-21

申请人： Li-Te S. Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te S. Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/40

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method of defining a gate structure for a MOSFET device featuring the employment of dual anti-reflective coating (ARC) layers to enhance gate structure resolution, and featuring a dry procedure for removal of all ARC layers avoiding the use of hot phosphoric acid, has been developed. After formation of a polysilicon layer on an underlying silicon dioxide gate insulator layer, a capping silicon oxide, a dielectric ARC layer, and an overlying organic ARC layer are deposited. A photoresist shape is formed and used as an etch mask to allow a first anisotropic RIE procedure to define the desired gate structure shape in the dual ARC layers and in the capping silicon oxide layer. After removal of the photoresist shape and the overlying organic ARC layer a second anisotropic RIE procedure is used to define a desired polysilicon gate structure, with the second anisotropic RIE procedure also resulting in the removal of the dielectric ARC shape. A final hydrofluoric acid type solution is then used to remove the capping silicon oxide shape as well as to remove the portions of the silicon dioxide gate insulator layer not covered by the polysilicon gate structure.

摘要翻译： 一种限定用于MOSFET器件的栅极结构的方法，其特征在于采用双抗反射涂层（ARC）层以增强栅极结构分辨率，并且具有用于去除所有ARC层的干法以避免使用热磷酸，具有 已经开发 在下面的二氧化硅栅极绝缘体层上形成多晶硅层之后，沉积覆盖氧化硅，电介质ARC层和上覆的有机ARC层。 形成光致抗蚀剂形状并用作蚀刻掩模，以允许第一各向异性RIE程序在双ARC层和封盖氧化硅层中限定所需的栅极结构形状。 在除去光致抗蚀剂形状和上覆的有机ARC层之后，使用第二各向异性RIE程序来限定期望的多晶硅栅极结构，其中第二各向异性RIE程序也导致去除电介质ARC形状。 然后使用最终的氢氟酸型溶液去除封端氧化硅形状以及去除未被多晶硅栅极结构覆盖的二氧化硅栅极绝缘体层的部分。

公开(公告)号：US20050118755A1

公开(公告)日：2005-06-02

申请号：US10999270

申请日：2004-11-29

申请人： Li-Te Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Fang-Chen Cheng ,  Huin-Jer Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/40

CPC分类号： H01L21/31116 ,  H01L21/32137 ,  H01L21/32139

摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.

摘要翻译： 在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。 在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。 使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。 使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

公开(公告)号：US06867084B1

公开(公告)日：2005-03-15

申请号：US10263541

申请日：2002-10-03

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L21/2652 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

摘要翻译： 描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。 首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。 然后将高k电介质材料衬垫沉积在所有暴露的表面上。 然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。 然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。 在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件 硅衬底。

公开(公告)号：US06869868B2

公开(公告)日：2005-03-22

申请号：US10318459

申请日：2002-12-13

申请人： Hsien-Kuang Chiu ,  Fang-Cheng Chen ,  Haur-Ywh Chen ,  Hun-Jan Tao ,  Yuan-Hung Chiu

发明人： Hsien-Kuang Chiu ,  Fang-Cheng Chen ,  Haur-Ywh Chen ,  Hun-Jan Tao ,  Yuan-Hung Chiu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/4763

CPC分类号： H01L29/785 ,  H01L21/28088 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66795

摘要： A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.

摘要翻译： 已经开发了形成用于平面MOSFET器件的复合栅极结构以及用于垂直双栅极FINFET器件的方法。 该方法具有由上覆硅栅极结构形状和下面的氮化钛栅极结构形状组成的复合栅极结构。 与仅由多晶硅形成的对应栅极结构相比，氮化钛部件允许较低的功函数，因此降低器件工作电压。 采用新颖的两步栅极结构定义方法，其特征在于用于定义多晶硅栅极结构形状的各向异性第一蚀刻工艺，随后是用于定义氮化钛栅极结构形状的湿式或干式同位素第二蚀刻工艺。

公开(公告)号：US20050127459A1

公开(公告)日：2005-06-16

申请号：US11048205

申请日：2005-02-01

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L21/2652 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

摘要翻译： 描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。 首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。 然后将高k电介质材料衬垫沉积在所有暴露的表面上。 然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。 然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。 在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件 硅衬底。

公开(公告)号：US20060154487A1

公开(公告)日：2006-07-13

申请号：US11033912

申请日：2005-01-11

申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21/8234 ,  H01L21/302

CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

公开(公告)号：US07301645B2

公开(公告)日：2007-11-27

申请号：US11053300

申请日：2005-02-07

申请人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

发明人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

IPC分类号： G01B11/02

CPC分类号： H01L22/20

摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.

摘要翻译： 提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

公开(公告)号：US20050106888A1

公开(公告)日：2005-05-19

申请号：US10714207

申请日：2003-11-14

申请人： Yuan-Hung Chiu ,  Ming-Ching Chang ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Ching Chang ,  Hun-Jan Tao

IPC分类号： G03F7/42 ,  H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01L21/31116 ,  G03F7/427 ,  H01L21/02046 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814

摘要： An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.

摘要翻译： 公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。 氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。 氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。 可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是 可以单独使用或与上述含卤素气体中的一种一起使用。 氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

公开(公告)号：US06764903B1

公开(公告)日：2004-07-20

申请号：US10427451

申请日：2003-04-30

申请人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a patterned target layer from a blanket target layer employs a pair of blanket hard mask layers laminated upon the blanket target layer. A patterned third mask layer is formed thereover. The method also employs four separate etch steps. One etch step is an anisotropic etch step for forming a patterned upper lying hard mask layer from the blanket upper lying hard mask layer. The patterned upper lying hard mask layer is then isotropically etched in a second etch step to form an isotropically etched patterned upper lying hard mask layer. The method is particularly useful for forming gate electrodes of diminished linewidths and enhanced dimensional control within semiconductor products.

摘要翻译： 从覆盖目标层形成图案化目标层的方法采用层叠在覆盖目标层上的一对覆盖层硬掩模层。 在其上形成图案化的第三掩模层。 该方法还采用四个独立的蚀刻步骤。 一个蚀刻步骤是用于从橡皮布上面的硬掩模层形成图案化的上卧硬掩模层的各向异性蚀刻步骤。 然后在第二蚀刻步骤中各向同性蚀刻图案化的上卧硬掩模层，以形成各向同性蚀刻的图案化的上面的硬掩模层。 该方法对于形成半导体产品中线宽减小和尺寸控制增强的栅电极特别有用。