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    Method of dual EPI process for semiconductor device
    2.
    发明授权
    Method of dual EPI process for semiconductor device 有权
    半导体器件的双重EPI工艺方法

    公开(公告)号：US08609497B2

    公开(公告)日：2013-12-17

    申请号：US12721399

    申请日：2010-03-10

    申请人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    发明人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823487 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

    摘要翻译： 本公开提供一种制造半导体器件的方法，该半导体器件包括分别在衬底的第一和第二区域上形成第一和第二栅极结构，在第一和第二栅极结构的侧壁上形成间隔物，间隔物由第一材料形成 在所述第一和第二栅极结构上形成覆盖层，所述覆盖层由不同于所述第一材料的第二材料形成，在所述第二区域上形成保护层以保护所述第二栅极结构，在所述第一栅极结构上移除所述覆盖层 门结构; 在所述第二区域上去除所述保护层，在所述第一区域中外延（epi）在所述衬底的暴露部分上生长半导体材料，以及通过蚀刻工艺去除所述第二栅极结构上的所述覆盖层，所述蚀刻工艺显示所述第二区域的蚀刻选择性 材料到第一种材料。

    Method of Dual EPI Process For Semiconductor Device
    3.
    发明申请
    Method of Dual EPI Process For Semiconductor Device 有权
    半导体器件的双重EPI工艺方法

    公开(公告)号：US20110201164A1

    公开(公告)日：2011-08-18

    申请号：US12721399

    申请日：2010-03-10

    申请人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    发明人： Han-Pin Chung ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang ,  Ming-Jie Huang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823487 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

    摘要翻译： 本公开提供一种制造半导体器件的方法，该半导体器件包括分别在衬底的第一和第二区域上形成第一和第二栅极结构，在第一和第二栅极结构的侧壁上形成间隔物，间隔物由第一材料形成 在所述第一和第二栅极结构上形成覆盖层，所述覆盖层由不同于所述第一材料的第二材料形成，在所述第二区域上形成保护层以保护所述第二栅极结构，在所述第一栅极结构上移除所述覆盖层 门结构; 在所述第二区域上去除所述保护层，在所述第一区域中外延（epi）在所述衬底的暴露部分上生长半导体材料，以及通过蚀刻工艺去除所述第二栅极结构上的所述覆盖层，所述蚀刻工艺显示所述第二区域的蚀刻选择性 材料到第一种材料。

    Method of forming a shallow trench isolation structure
    4.
    发明授权
    Method of forming a shallow trench isolation structure 有权
    形成浅沟槽隔离结构的方法

    公开(公告)号：US07947551B1

    公开(公告)日：2011-05-24

    申请号：US12892331

    申请日：2010-09-28

    申请人： Sen-Hong Syue ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang

    发明人： Sen-Hong Syue ,  Bor Chiuan Hsieh ,  Shiang-Bau Wang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/02337 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02356 ,  H01L21/76224

    摘要： An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.

    摘要翻译： 本公开的实施例包括形成浅沟槽隔离结构的方法。 提供基板。 衬底包括顶表面。 形成沟槽以从顶表面延伸到衬底中。 沟槽具有侧壁和底面。 在侧壁和底表面上形成硅衬层。 可流动介电材料填充在沟槽中。 进行退火处理以使可流动电介质材料致密化并同时将硅衬层转化为氧化硅层。

    ETCHING PROCESS TO AVOID POLYSILICON NOTCHING
    5.
    发明申请
    ETCHING PROCESS TO AVOID POLYSILICON NOTCHING 有权
    蚀刻过程避免多晶硅缺口

    公开(公告)号：US20060154487A1

    公开(公告)日：2006-07-13

    申请号：US11033912

    申请日：2005-01-11

    申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    IPC分类号： H01L21/8234 ,  H01L21/302

    CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

    摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

    摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

    Multilayer hard mask
    6.
    发明授权
    Multilayer hard mask 有权
    多层硬掩模

    公开(公告)号：US08372755B2

    公开(公告)日：2013-02-12

    申请号：US12686866

    申请日：2010-01-13

    申请人： Shiang-Bau Wang ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Hun-Jan Tao

    IPC分类号： H01L21/302 ,  H01L29/66

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有 厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

    In-situ critical dimension measurement
    8.
    发明授权
    In-situ critical dimension measurement 有权
    原位临界尺寸测量

    公开(公告)号：US07301645B2

    公开(公告)日：2007-11-27

    申请号：US11053300

    申请日：2005-02-07

    申请人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

    发明人： Shiang-Bau Wang ,  Yuan-Hung Chiu ,  Hun-Jan Tao ,  Chao-Tzung Tsai

    IPC分类号： G01B11/02

    CPC分类号： H01L22/20

    摘要： A method of monitoring a critical dimension of a structural element in an integrated circuit is provided comprising the following steps: collecting an optical interference endpoint signal produced during etching one or more layers to form the structural element; and determining based upon the optical interference endpoint signal the critical dimension of the structural element.

    摘要翻译： 提供一种监测集成电路中的结构元件的关键尺寸的方法，包括以下步骤：收集在蚀刻一个或多个层期间产生的光学干涉终点信号以形成结构元件; 以及基于所述光学干涉终点信号确定所述结构元件的临界尺寸。

    Multilayer Hard Mask
    9.
    发明申请
    Multilayer Hard Mask 有权
    多层硬面膜

    公开(公告)号：US20110171804A1

    公开(公告)日：2011-07-14

    申请号：US12686866

    申请日：2010-01-13

    申请人： Shiang-Bau Wang ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供半导体衬底; 在所述半导体衬底上形成栅极材料层; 在所述栅极材料层上形成多层硬掩模层，其中所述多层硬掩模层包括多个膜堆叠，每个膜堆叠具有氧化硅层和含碳材料层，每个膜堆叠具有 厚度等于或小于约10埃; 图案化多层硬掩模层，形成多硬掩模层的开口; 蚀刻多层硬掩模层的开口内的栅极材料层，形成栅极结构; 对所述半导体衬底进行倾斜角度离子注入工艺，其中所述多层硬掩模层的第一剩余厚度小于第一厚度; 然后对所述半导体衬底进行外延生长，其中所述多层硬掩模层的第二剩余厚度大于第二厚度。

    Etching process to avoid polysilicon notching
    10.
    发明授权
    Etching process to avoid polysilicon notching 有权
    蚀刻工艺避免多晶硅切口

    公开(公告)号：US07109085B2

    公开(公告)日：2006-09-19

    申请号：US11033912

    申请日：2005-01-11

    申请人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    发明人： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

    摘要： A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

    摘要翻译： 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。