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公开(公告)号：US5708395A
公开(公告)日：1998-01-13
申请号：US800236
申请日：1997-02-12
CPC分类号： H03L7/0991
摘要： A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference signal PREF multiplied by sixteen (32/2) is generated by the digital oscillation circuit.
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公开(公告)号：US5789985A
公开(公告)日：1998-08-04
申请号：US621607
申请日：1996-03-22
CPC分类号： H03L7/0991
摘要： A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference signal PREF multiplied by sixteen (32/2) is generated by the digital oscillation circuit.
摘要翻译： 将外部提供的参考信号PREF的频率相乘的倍频装置包括数字控制的振荡电路，其包括由环形配置中的三十二个反相电路形成的环形振荡器，该环形振荡器适于产生十六个时钟信号， 周期，是每个反相电路的反相时间的三十二倍，是反相电路反相时间的两倍的相位间隔，并产生具有与频率控制数据CD相对应的周期的输出信号POUT，该周期以相位差的分辨率 时钟信号的时间;计数器/数据锁存电路，用于对参考信号PREF的一个周期内由环形振荡器释放的时钟信号RCK进行计数，并将计数值的频率控制数据CD传送到数字振荡电路;以及 控制电路，其控制电路的运行，使得具有频率的振荡输出信号POUT 通过数字振荡电路产生参考信号PREF乘以十六（32/2）的通量。
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3.发明授权Direct-current power supply circuit having control sections with at least one control section having priority over another control section 失效具有控制部分的直流电源电路具有至少一个控制部分优先于另一个控制部分公开(公告)号：US06262903B1
公开(公告)日：2001-07-17
申请号：US09471231
申请日：1999-12-23
IPC分类号： H02M7217
CPC分类号： H02M3/33576 , H02M7/1557
摘要： A direct-current power supply circuit, incorporated in an IC card, includes a coil for receiving an amplitude-modulated signal from an external device through electromagnetic induction. A full-wave rectifying circuit rectifies the amplitude-modulated signal received by the coil. The rectified output signal is used to charge a smoothing capacitor. A clamp circuit controls the terminal voltage of the smoothing capacitor to a predetermined level so as to produce a power supply voltage. The clamp circuit controls an output transistor to stabilize the power supply voltage to a constant level. Furthermore, the direct-current power supply circuit includes a short-circuit preventing circuit to forcibly turn off the output transistor when the electric potential difference between both ends of the coil is smaller than a predetermined value, thereby preventing the power supply voltage from suddenly decreasing due to delay of operation of the circuit elements when the coil output becomes zero due to amplitude modulation.
摘要翻译： 并入IC卡中的直流电源电路包括用于通过电磁感应从外部装置接收幅度调制信号的线圈。 全波整流电路对由线圈接收的幅度调制信号进行整流。 整流输出信号用于对平滑电容器充电。 钳位电路将平滑电容器的端子电压控制到预定电平，以产生电源电压。 钳位电路控制输出晶体管，以将电源电压稳定在一定水平。 此外，直流电源电路包括短路防止电路，当线圈两端的电位差小于预定值时强制关断输出晶体管，从而防止电源电压突然下降 由于振幅调制时线圈输出变为零时由于电路元件的工作延迟。
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4.发明授权Semiconductor strain sensor having improved resistance to bonding strain effects 失效半导体应变传感器具有改善的耐结合应变效应
公开(公告)号：US5408112A
公开(公告)日：1995-04-18
申请号：US91068
申请日：1993-07-14
申请人： Akira Tai , Toshitaka Yamada , Yoshinori Fujihashi , Tsuyoshi Fukada , Hirohito Shioya , Yoshimi Yoshino , Hiroshige Sugito
发明人： Akira Tai , Toshitaka Yamada , Yoshinori Fujihashi , Tsuyoshi Fukada , Hirohito Shioya , Yoshimi Yoshino , Hiroshige Sugito
CPC分类号： G01B7/20 , G01P15/0802 , G01P15/123 , G01P2015/0828 , H01L2224/48091 , H01L2924/10253
摘要： A semiconductor strain sensor includes a base, a peripheral section, a central section and a flexible beam. The peripheral section is bent to the base. Bonding strain is generated at a bonding portion between the base and the peripheral section. The central section extends from the peripheral section. The flexible beam extends from the central section and includes a strain detecting element. The strain detecting element changes its electric characteristic when strain is applied thereto. A thickness of the flexible beam is thinner than that of the central section. The bonding strain is transmitted from the bonding portion to the strain detecting element through a transmission path. The transmission path is bent. The bonding strain is attenuated because it is dispersed at a bending portion of the transmission path. The sensor accurately detects the strain to be detected without a bad influence of the bonding strain.
摘要翻译： 半导体应变传感器包括基座，外围部分，中心部分和柔性梁。 外围部分弯曲到基部。 在基部和周边部之间的接合部分产生接合应变。 中央部分从外围部分延伸。 柔性梁从中心部分延伸并且包括应变检测元件。 当应变应变时，应变检测元件改变其电特性。 柔性梁的厚度比中央部分的厚度薄。 接合应变通过传输路径从结合部分传递到应变检测元件。 传输路径弯曲。 粘合应变由于分散在传输路径的弯曲部分而衰减。 传感器精确地检测待检测的应变，而不受粘合应变的不良影响。
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公开(公告)号：US4897658A
公开(公告)日：1990-01-30
申请号：US170358
申请日：1988-03-18
摘要： An analog-to-digital converter of the successive-approximation type has a successive-approximation logic circuit for successively generating selection signals defined by significant bits in a digital value, a string of high resistance elements to provide voltage dividers for successively dividing a reference voltage into divided voltages, a switch matrix circuit for generating the divided voltages when activated in response to the selection signals, a comparator for successively comparing an analog level with the divided voltages and for generating comparison signals respectively indicative of the significant bits and an output circuit for generating an output digital signal defined by the significant bits when applied with all the comparison signals, the output circuit being associated with the logic circuit for causing it to generate the selection signals in response to the comparison signals. A string of low resistance elements are provided to apply therethrough the reference voltage to at least one of the voltage dividers during a short period of time immediately after the one of the voltage dividers has been activated.
摘要翻译： 逐次近似型的模数转换器具有逐次逼近逻辑电路，用于连续产生由数字值中的有效位定义的选择信号，一组高电阻元件，以提供分压器，用于连续分频参考电压 分压电路，用于响应于选择信号而被激活时产生分压的开关矩阵电路;比较器，用于连续地将模拟电平与分压电压进行比较，并产生分别表示有效位的比较信号和输出电路， 当应用所有比较信号时，产生由有效位定义的输出数字信号，输出电路与逻辑电路相关联，以使其响应于比较信号产生选择信号。 提供一串低电阻元件，用于在紧接在其中一个分压器被激活之后的短时间内将参考电压施加到至少一个分压器。
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