公开(公告)号：US4314215A

公开(公告)日：1982-02-02

申请号：US168324

申请日：1980-07-11

申请人： Shigeo Tanji ,  Noboru Wakatsuki ,  Hideki Tominaga

发明人： Shigeo Tanji ,  Noboru Wakatsuki ,  Hideki Tominaga

IPC分类号： H03H9/145 ,  H03H3/08 ,  H03H9/02 ,  H03H9/05 ,  H03H9/64 ,  H03H9/25 ,  H03H9/42

CPC分类号： H03H9/6496 ,  H03H9/02874 ,  H03H9/0296 ,  H03H9/058

摘要： A surface acoustic wave filter device in which a capacitative coupling means is provided to couple at least one of the terminals of the SAW input transducer to at least one of the terminals of the output transducer, in order to equalize the levels of signals which are induced on the pair of output terminals of said output transducer without assuming the form of surface acoustic waves. The stray inductive coupling which normally occurs between the input and output terminals of the SAW filter degrades filter performance. Since the inductive coupling to the two output terminals is normally unequal, the inductively coupled unfiltered signals cannot be completely rejected by a balanced differential amplifier. By equalizing the levels of unfiltered signals at the output terminal, effective rejection by a differential amplifier is possible.

摘要翻译： 一种表面声波滤波器装置，其中提供电容耦合装置以将SAW输入换能器的至少一个端子耦合到输出换能器的至少一个端子，以便均衡感应的信号电平 在所述输出换能器的一对输出端子上，而不采取表面声波的形式。 通常发生在SAW滤波器的输入和输出端子之间的杂散电感耦合会降低滤波器性能。 由于与两个输出端子的电感耦合通常是不相等的，电感耦合未滤波信号不能被平衡差分放大器完全拒绝。 通过均衡输出端子上未滤波信号的电平，差分放大器的有效抑制是可能的。

公开(公告)号：US09420210B2

公开(公告)日：2016-08-16

申请号：US12996969

申请日：2009-06-10

申请人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

发明人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

IPC分类号： H04N5/235 ,  H04N5/378 ,  H04N5/3745 ,  H01L27/148 ,  H04N5/357

CPC分类号： H04N5/378 ,  H01L27/14843 ,  H04N5/3575 ,  H04N5/37452

摘要： A burst reading memory section (200) and continuous reading memory section (210) are independently provided for each of the two-dimensionally arrayed pixels (10). The burst reading memory section (200) has capacitors (25001-25104) capable of holding a plurality of signals. The continuous reading memory section (210) has only one capacitor 213. Signal output lines for the two memory sections are separately provided. When a signal produced by photoelectric conversion at the pixel (10) is outputted on a pixel output line (14), the signal can be simultaneously written in the capacitors at both memory sections (200, 201), after which the signals can be separately extracted to the outside at different timings. Therefore, a series of images taken at extremely short intervals of time during a short period of time can be obtained at an arbitrary timing without impeding a continuous image-acquiring operation at a low frame rate. Accordingly, both an ultrahigh-speed imaging operation having a limitation on the number of frames and an imaging that is rather slow but has no limitation on the number of frames can be simultaneously performed.

摘要翻译： 对于二维排列的像素（10）中的每一个，独立地提供突发读取存储器部分（200）和连续读取存储器部分（210）。 脉冲串读取存储部分（200）具有能够保持多个信号的电容器（25001-25104）。 连续读取存储部分（210）仅具有一个电容器213.两个存储器部分的信号输出线被单独提供。 当在像素（10）上通过光电转换产生的信号在像素输出线（14）上输出时，该信号可以同时写入两个存储部分（200,201）的电容器中，之后信号可以分开 在不同的时间提取到外面。 因此，可以在任意的时刻以非常短的时间间隔拍摄的一系列图像，而不会以低帧率阻碍连续的图像获取操作。 因此，可以同时执行对帧数量的限制和相当慢但对帧数量没有限制的成像的超高速成像操作。

公开(公告)号：US08541731B2

公开(公告)日：2013-09-24

申请号：US12996613

申请日：2009-06-10

申请人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

发明人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

IPC分类号： H01L27/146 ,  H04N5/335

CPC分类号： H04N5/335 ,  H01L27/14643 ,  H04N5/355 ,  H04N5/378

摘要： A pixel output line is provided for each of the pixels two-dimensionally arrayed in a pixel area. The pixel output lines are extended to a memory area, and a memory unit is connected to each of those lines. The memory unit includes a writing-side transistor, a reading-side transistor and a plurality of memory sections for holding signals for 104 image frames. A photocharge storage operation is simultaneously performed at all the pixels, and the thereby produced signals are outputted to the pixel output lines. In the memory unit, with the writing-side transistor in the ON state, the sampling transistor of a different memory section is sequentially turned on for each exposure cycle so as to sequentially hold a signal in the capacitor of each memory section. After a burst imaging operation is completed, all the pixel signals are sequentially read. Unlike CCDs, the present device does not simultaneously drive all gate loads, so that it can be driven at high speeds with low power consumption. Thus, the burst imaging can be performed at higher speeds than ever before.

摘要翻译： 为像素区域中二维排列的每个像素提供像素输出线。 像素输出线被扩展到存储区域，并且存储器单元连接到这些行中的每一行。 存储单元包括写入侧晶体管，读取侧晶体管和用于保持104个图像帧的信号的多个存储器部分。 在所有像素处同时执行光电荷存储操作，并且由此产生的信号被输出到像素输出线。 在存储器单元中，在写入侧晶体管处于导通状态的情况下，对于每个曝光周期，不同存储器部分的采样晶体管顺序地导通，以便顺序地保持每个存储器部分的电容器中的信号。 在突发图像操作完成之后，依次读取所有像素信号。 与CCD不同，本装置不会同时驱动所有栅极负载，因此可以以低功耗高速驱动。 因此，可以以比以往更高的速度执行突发成像。

公开(公告)号：US08269838B2

公开(公告)日：2012-09-18

申请号：US12676532

申请日：2008-09-04

申请人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

发明人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

IPC分类号： H04N5/228 ,  H04N5/335

CPC分类号： H04N5/378 ,  H04N5/3415 ,  H04N5/374

摘要： A pixel output line (14) is independently provided for each of the pixels arranged in a two-dimensionally array within a pixel area so that pixel signals can be sequentially written in a plurality of memory sections (22) through the pixel output lines (14). When a plurality of frames of pixel signals are held in the memory sections (22), the pixel signals corresponding to two arbitrarily selected frames are read and respectively stored in sample-and-hold circuits (61 and 62), and their difference is obtained. Then, the difference signals corresponding to a predetermined range of the image are integrated, and the integrated value is compared with a threshold. If the integrated value exceeds the threshold, it is presumed that a change in an imaging object has occurred, and a pulse generation circuit (66) generates a trigger signal. By controlling the discontinuation and other imaging actions according to this trigger signal, it is possible to correctly take high-speed images of the situation before or after the occurrence of an objective phenomenon.

摘要翻译： 像素输出线（14）被独立地设置在像素区域内以二维阵列布置的每个像素，使得可以通过像素输出线（14）将像素信号顺序地写入多个存储器部分（22） ）。 当多个像素信号帧被保持在存储部分（22）中时，对应于两个任意选择的帧的像素信号被读取并分别存储在采样和保持电路（61和62）中，并且获得它们的差异 。 然后，对应于图像的预定范围的差分信号被积分，并将积分值与阈值进行比较。 如果积分值超过阈值，则假设成像对象发生变化，脉冲发生电路（66）产生触发信号。 通过根据该触发信号控制中断和其他成像动作，可以在目标现象发生之前或之后正确地拍摄情况。

公开(公告)号：US20110085066A1

公开(公告)日：2011-04-14

申请号：US12996969

申请日：2009-06-10

申请人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

发明人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

IPC分类号： H04N5/335

CPC分类号： H04N5/378 ,  H01L27/14843 ,  H04N5/3575 ,  H04N5/37452

摘要： A burst reading memory section (200) and continuous reading memory section (210) are independently provided for each of the two-dimensionally arrayed pixels (10). The burst reading memory section (200) has capacitors (25001-25104) capable of holding a plurality of signals. The continuous reading memory section (210) has only one capacitor 213. Signal output lines for the two memory sections are separately provided. When a signal produced by photoelectric conversion at the pixel (10) is outputted on a pixel output line (14), the signal can be simultaneously written in the capacitors at both memory sections (200, 201), after which the signals can be separately extracted to the outside at different timings. Therefore, a series of images taken at extremely short intervals of time during a short period of time can be obtained at an arbitrary timing without impeding a continuous image-acquiring operation at a low frame rate. Accordingly, both an ultrahigh-speed imaging operation having a limitation on the number of frames and an imaging that is rather slow but has no limitation on the number of frames can be simultaneously performed.

摘要翻译： 对于二维排列的像素（10）中的每一个，独立地提供突发读取存储器部分（200）和连续读取存储器部分（210）。 脉冲串读取存储部分（200）具有能够保持多个信号的电容器（25001-25104）。 连续读取存储部分（210）仅具有一个电容器213.两个存储器部分的信号输出线被单独提供。 当在像素（10）上通过光电转换产生的信号在像素输出线（14）上输出时，该信号可以同时写入两个存储器部分（200,201）的电容器中，之后信号可以分开 在不同的时间提取到外面。 因此，可以在任意的时刻以非常短的时间间隔拍摄的一系列图像，而不会以低帧率阻碍连续的图像获取操作。 因此，可以同时执行对帧数量的限制和相当慢但对帧数量没有限制的成像的超高速成像操作。

公开(公告)号：US09030582B2

公开(公告)日：2015-05-12

申请号：US13983975

申请日：2011-02-08

申请人： Shigetoshi Sugawa ,  Hideki Tominaga ,  Kenji Takubo ,  Yasushi Kondo

发明人： Shigetoshi Sugawa ,  Hideki Tominaga ,  Kenji Takubo ,  Yasushi Kondo

IPC分类号： H04N3/14 ,  H04N5/335 ,  H04N5/357 ,  H04N5/3745 ,  H04N5/378

CPC分类号： H04N5/357 ,  H04N5/3575 ,  H04N5/3745 ,  H04N5/37452 ,  H04N5/378

摘要： A transistor (24) which acts as a load-current source for a source follower amplifying transistor (22) for outputting a pixel signal to a pixel output line (40) is provided in each picture element (10), whereby a high bias current is prevented from passing through the high-resistance pixel output line (40), so that a variation in an offset voltage among picture elements is suppressed. Inclusion of the high-resistance pixel output line (40) into the source follower amplification circuit is also avoided, whereby the gain characteristics are prevented from deterioration. Thus, the S/N ratio of the picture element is improved so as to enhance the quality of the images.

摘要翻译： 作为用于将像素信号输出到像素输出线（40）的源极跟随放大晶体管（22）的负载电流源的晶体管（24）设置在每个像素（10）中，由此高偏置电流 被阻止通过高电阻像素输出线（40），从而抑制像素之间的偏移电压的变化。 还避免了将高电阻像素输出线（40）包括在源极跟随器放大电路中，从而防止增益特性的劣化。 因此，提高了像素的S / N比，从而提高了图像的质量。

公开(公告)号：US20120112255A1

公开(公告)日：2012-05-10

申请号：US13382878

申请日：2010-06-23

申请人： Yasushi Kondo ,  Hideki Tominaga ,  Kenji Takubo ,  Ryuta Hirose ,  Shigetoshi Sugawa ,  Hideki Mutoh

发明人： Yasushi Kondo ,  Hideki Tominaga ,  Kenji Takubo ,  Ryuta Hirose ,  Shigetoshi Sugawa ,  Hideki Mutoh

IPC分类号： H01L31/02

CPC分类号： H01L27/14603 ,  H01L27/14607 ,  H01L27/14609 ,  H01L27/1461

摘要： A floating diffusion region is formed at an edge of a light-receiving surface of an embedded photodiode, with a transfer gate electrode located therebetween. A first region, with radially extending portions centered on the FD region, and a second region, located to the outside of the first region, are created in the substantially sector-shaped light-receiving surface. A dopant whose conductivity type is the same as the signal charges to be collected in the first region are introduced, whereby an electric field for moving the signal charges from the radially extending sections towards the center is created due to a three-dimensional field effect. As a result, the charge-transfer time is reduced. Additionally, since a circuit element in the subsequent stage can be placed adjacent to the floating diffusion region, the parasitic capacitance of the floating diffusion region can be reduced and a highly sensitive element can be obtained.

摘要翻译： 在嵌入式光电二极管的光接收表面的边缘处形成浮动扩散区，其中位于其间的传输栅电极。 在大致扇形的光接收表面上形成有以FD区域为中心的径向延伸部分的第一区域和位于第一区域外部的第二区域。 引入导电类型与要在第一区域中收集的信号电荷相同的掺杂剂，由此由于三维场效应，产生用于使信号从径向延伸部分向中心移动的电场。 结果，电荷转移时间减少。 此外，由于随后阶段的电路元件可以放置在与浮动扩散区域相邻的位置，所以可以减小浮动扩散区域的寄生电容，并且可以获得高灵敏度的元件。

公开(公告)号：US20110084197A1

公开(公告)日：2011-04-14

申请号：US12996613

申请日：2009-06-10

申请人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

发明人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

IPC分类号： H01L27/146

CPC分类号： H04N5/335 ,  H01L27/14643 ,  H04N5/355 ,  H04N5/378

摘要： A pixel output line is provided for each of the pixels two-dimensionally arrayed in a pixel area. The pixel output lines are extended to a memory area, and a memory unit is connected to each of those lines. The memory unit includes a writing-side transistor, a reading-side transistor and a plurality of memory sections for holding signals for 104 image frames. A photocharge storage operation is simultaneously performed at all the pixels, and the thereby produced signals are outputted to the pixel output lines. In the memory unit, with the writing-side transistor in the ON state, the sampling transistor of a different memory section is sequentially turned on for each exposure cycle so as to sequentially hold a signal in the capacitor of each memory section. After a burst imaging operation is completed, all the pixel signals are sequentially read. Unlike CCDs, the present device does not simultaneously drive all gate loads, so that it can be driven at high speeds with low power consumption. Thus, the burst imaging can be performed at higher speeds than ever before.

摘要翻译： 为像素区域中二维排列的每个像素提供像素输出线。 像素输出线被扩展到存储区域，并且存储器单元连接到这些行中的每一行。 存储单元包括写入侧晶体管，读取侧晶体管和用于保持104个图像帧的信号的多个存储器部分。 在所有像素处同时执行光电荷存储操作，并且由此产生的信号被输出到像素输出线。 在存储器单元中，在写入侧晶体管处于导通状态的情况下，对于每个曝光周期，不同存储器部分的采样晶体管顺序地导通，以便顺序地保持每个存储器部分的电容器中的信号。 在突发图像操作完成之后，依次读取所有像素信号。 与CCD不同，本装置不会同时驱动所有栅极负载，因此可以以低功耗高速驱动。 因此，可以以比以往更高的速度执行突发成像。

公开(公告)号：US5482001A

公开(公告)日：1996-01-09

申请号：US318251

申请日：1994-10-05

申请人： Tomoko Katoono ,  Hideki Tominaga

发明人： Tomoko Katoono ,  Hideki Tominaga

IPC分类号： G02B1/02 ,  C30B9/00 ,  C30B29/30 ,  C30B15/02

CPC分类号： C30B9/00 ,  C30B29/30

摘要： A process for producing a lithium niobate single crystal which comprises restricting the variation of the Curie point due to the effect of impurities within a specific range in the accurate evaluation of the composition of the lithium niobate single crystal by the use of the Curie point. To produce a lithium niobate single crystal by using, singly or in combination, lithium carbonate having a purity of 99.99% or higher and simultaneously satisfying the condition that the contents therein of elements Na, K, Mg, and A1 are 5.0 ppm or less, 2.0 ppm or less, 0.5 ppm or less, and 0.9 ppm or less, respectively, and niobium pentoxide having a purity of 99.99% or higher and simultaneously satisfying the condition that the contents therein of elements Na, K, Mg, Al, and Cl are 3.0 ppm or less, 1.0 ppm or less, 0.5 ppm or less, 0.9 ppm or less, and 3.0 ppm or less, respectively, according to an ordinary method.

摘要翻译： 一种铌酸锂单晶的制造方法，其特征在于，通过使用居里点来精确评价铌酸锂单晶的组成，可以限制由于杂质的影响而产生的居里点的变化。 为了通过单独或组合使用纯度为99.99％以上的碳酸锂并同时满足元素Na，K，Mg和Al的含量为5.0ppm以下的条件来制造铌酸锂单晶， 分别为2.0ppm以下，0.5ppm以下，0.9ppm以下，以及纯度为99.99％以上的五氧化二铌，同时满足元素Na，K，Mg，Al，Cl的含量 根据常规方法分别为3.0ppm以下，1.0ppm以下，0.5ppm以下，0.9ppm以下，3.0ppm以下。

公开(公告)号：US08988571B2

公开(公告)日：2015-03-24

申请号：US12676562

申请日：2008-09-04

申请人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

发明人： Shigetoshi Sugawa ,  Yasushi Kondo ,  Hideki Tominaga

IPC分类号： H04N5/335 ,  H04N5/355 ,  H04N5/3745 ,  H04N5/378

CPC分类号： H04N5/35527 ,  H04N5/37452 ,  H04N5/378

摘要： A pixel area with a two-dimensional array of pixels (10) each including a photodiode and a memory area (3a) on which memory sections for holding signals produced by the pixels for continuously recordable frames are separately provided on a semiconductor substrate. All the pixels simultaneously perform a photocharge storage operation, and the signals produced by the photocharge storage are extracted in parallel through mutually independent pixel output lines (14). In a plurality of memory sections connected to one pixel output line, a sample-and-hold transistor of a different memory section is turned on for each exposure cycle so as to sequentially hold signals in a capacitor of each memory section. After the continuous imaging is completed, all the pixel are sequentially read. Unlike CCD cameras, the present sensor does not simultaneously drive all the gate loads. Therefore, the sensor consumes less power yet can be driven at high speeds. The separation between the memory area and pixel area prevents signals from deterioration due to an intrusion of excessive photocharges. As a result, the sensor can perform imaging operations at higher speeds than ever before and yet capture images with higher qualities.

摘要翻译： 具有二维像素阵列（10）的像素区域，每个像素（10）包括光电二极管和存储区域（3a），在半导体衬底上分别设置有用于保持用于连续可记录帧的像素产生的信号的存储部分。 所有像素同时进行光电荷存储操作，并且通过相互独立的像素输出线（14）并行提取由光电荷存储产生的信号。 在连接到一个像素输出线的多个存储器部分中，对于每个曝光周期，不同存储器部分的采样和保持晶体管导通，以便顺序地保持每个存储器部分的电容器中的信号。 连续成像完成后，依次读取所有像素。 与CCD相机不同，本传感器不会同时驱动所有的栅极负载。 因此，传感器消耗较少的功率，但可以高速驱动。 存储区域和像素区域之间的分离可以防止信号由于过多的光电荷的入侵而恶化。 因此，传感器可以以比以往更高的速度进行成像操作，并且捕获具有更高质量的图像。