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    Gated semiconductor device and method of fabricating same
    3.
    发明授权
    Gated semiconductor device and method of fabricating same 有权
    门式半导体器件及其制造方法

    公开(公告)号：US07700473B2

    公开(公告)日：2010-04-20

    申请号：US11784633

    申请日：2007-04-09

    申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

    摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

    摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧上的尺寸上横向减小以产生底切。

    Gated semiconductor device and method of fabricating same
    4.
    发明申请
    Gated semiconductor device and method of fabricating same 有权
    门式半导体器件及其制造方法

    公开(公告)号：US20080248620A1

    公开(公告)日：2008-10-09

    申请号：US11784633

    申请日：2007-04-09

    申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

    摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

    摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

    Gated semiconductor device and method of fabricating same
    5.
    发明授权
    Gated semiconductor device and method of fabricating same 有权
    门式半导体器件及其制造方法

    公开(公告)号：US08227850B2

    公开(公告)日：2012-07-24

    申请号：US12723381

    申请日：2010-03-12

    申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

    摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

    摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

    Gated Semiconductor Device and Method of Fabricating Same
    6.
    发明申请
    Gated Semiconductor Device and Method of Fabricating Same 有权
    门控半导体器件及其制造方法

    公开(公告)号：US20100171167A1

    公开(公告)日：2010-07-08

    申请号：US12723381

    申请日：2010-03-12

    申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

    摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

    摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

    Strap-Contact Scheme for Compact Array of Memory Cells
    7.
    发明申请
    Strap-Contact Scheme for Compact Array of Memory Cells 有权
    紧凑型存储单元阵列的带式接触方案

    公开(公告)号：US20100008141A1

    公开(公告)日：2010-01-14

    申请号：US12170186

    申请日：2008-07-09

    申请人： Yi-Shin Chu ,  Shih-Wei Wang

    发明人： Yi-Shin Chu ,  Shih-Wei Wang

    IPC分类号： G11C16/04 ,  G11C16/00

    CPC分类号： H01L27/11521 ,  H01L27/0207 ,  H01L27/11519 ,  H01L29/66825 ,  H01L29/7881

    摘要： A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps.

    摘要翻译： 具有用于存储单元阵列的多个带接触配置的半导体器件。 提供了具有与位线，控制栅极线，擦除栅极线，公共源极线和字线互连的存储器单元的阵列。 在说明性实施例的一个方面，带接触走廊在阵列上以n位线间隔（n> 1）间隔开。 带接触走廊包括带状接触单元，其提供控制栅极线，擦除栅极线，公共源极线和字线及其各自的带之间的电互连。

    Strap-contact scheme for compact array of memory cells
    8.
    发明授权
    Strap-contact scheme for compact array of memory cells 有权
    紧凑阵列存储单元的带式接触方案

    公开(公告)号：US07701767B2

    公开(公告)日：2010-04-20

    申请号：US12170186

    申请日：2008-07-09

    申请人： Yi-Shin Chu ,  Shih-Wei Wang

    发明人： Yi-Shin Chu ,  Shih-Wei Wang

    IPC分类号： G11C16/04 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/0207 ,  H01L27/11519 ,  H01L29/66825 ,  H01L29/7881

    摘要： A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps.

    摘要翻译： 具有用于存储单元阵列的多个带接触配置的半导体器件。 提供了具有与位线，控制栅极线，擦除栅极线，公共源极线和字线互连的存储器单元的阵列。 在说明性实施例的一个方面，带接触走廊在阵列上以n位线间隔（n> 1）间隔开。 带接触走廊包括带状接触单元，其提供控制栅极线，擦除栅极线，公共源极线和字线及其各自的带之间的电互连。

    Method for forming CMOS image sensors
    9.
    发明授权
    Method for forming CMOS image sensors 有权
    CMOS图像传感器的形成方法

    公开(公告)号：US08987033B2

    公开(公告)日：2015-03-24

    申请号：US13196560

    申请日：2011-08-02

    申请人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

    发明人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

    IPC分类号： H01L21/00 ,  H01L27/146

    CPC分类号： H01L27/1463

    摘要： A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.

    摘要翻译： 一种方法包括在衬底上形成阻挡层，并蚀刻阻挡层以在阻挡层中形成沟槽。 形成介电层，其中电介质层包括阻挡层上的第一部分和沟槽中的第二部分。 在形成介电层的步骤之后，进行注入以将杂质注入衬底以形成深阱区。 在植入之后，去除介电层和阻挡层。

    Method for Forming CMOS Image Sensors
    10.
    发明申请
    Method for Forming CMOS Image Sensors 有权
    CMOS图像传感器的形成方法

    公开(公告)号：US20130034929A1

    公开(公告)日：2013-02-07

    申请号：US13196560

    申请日：2011-08-02

    申请人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

    发明人： Ching-Chung Su ,  Shih-Chang Liu ,  Shih Pei Chou ,  Chia-Shiung Tsai ,  Chun-Tsung Kuo ,  Wen-I Hsu ,  Yi-Shin Chu

    IPC分类号： H01L31/18

    CPC分类号： H01L27/1463

    摘要： A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed.

    摘要翻译： 一种方法包括在衬底上形成阻挡层，并蚀刻阻挡层以在阻挡层中形成沟槽。 形成介电层，其中电介质层包括阻挡层上的第一部分和沟槽中的第二部分。 在形成介电层的步骤之后，进行注入以将杂质注入衬底以形成深阱区。 在植入之后，去除介电层和阻挡层。