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    MOS transistor
    3.
    发明申请
    MOS transistor 审中-公开
    MOS晶体管

    公开(公告)号：US20070228464A1

    公开(公告)日：2007-10-04

    申请号：US11748479

    申请日：2007-05-14

    申请人： Hsiang-Ying Wang ,  Chin-Cheng Chien ,  Tsai-Fu Hsiao ,  Ming-Yen Chien ,  Chao-Chun Chen

    发明人： Hsiang-Ying Wang ,  Chin-Cheng Chien ,  Tsai-Fu Hsiao ,  Ming-Yen Chien ,  Chao-Chun Chen

    IPC分类号： H01L29/772

    CPC分类号： H01L21/26506 ,  H01L21/2658 ,  H01L29/6659

    摘要： A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.

    摘要翻译： 一种形成MOS晶体管的方法，其中执行共注入以将注入植入源区域和漏区域或晕圈注入区域中，以有效地防止掺杂剂在源区和漏区中的过度扩散或 用于获得良好的接合曲线并改善短沟道效应。 植入物包括碳，烃或烃的衍生物，例如选自C，C≡H，H +和/或C（C） 其中x为1〜10的数，y为4〜20的数，n为1〜10的数，n为0〜 数量为1〜1000。

    Method for forming a junction region of a semiconductor device
    4.
    发明授权
    Method for forming a junction region of a semiconductor device 有权
    用于形成半导体器件的接合区域的方法

    公开(公告)号：US07060547B2

    公开(公告)日：2006-06-13

    申请号：US10764437

    申请日：2004-01-27

    申请人： Yu-Kun Chen ,  Neng-Hui Yang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang

    发明人： Yu-Kun Chen ,  Neng-Hui Yang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/2256 ,  H01L21/28176 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.

    摘要翻译： 公开了一种用于形成半导体器件的接合区域的方法。 该方法的步骤包括提供半导体衬底。 栅极结构形成在半导体衬底上。 将掺杂剂注入到半导体衬底中以形成结区域。 在栅极结构和半导体衬底上形成绝缘体层。 对绝缘体层进行含碳等离子体处理。 在栅极结构的侧壁上形成间隔物，并且将掺杂剂注入到半导体衬底中以在接合区域旁边形成源极/漏极区域。 对半导体基板进行热处理。

    Method of manufacturing metal-oxide-semiconductor transistor
    7.
    发明授权
    Method of manufacturing metal-oxide-semiconductor transistor 有权
    制造金属氧化物半导体晶体管的方法

    公开(公告)号：US07435658B2

    公开(公告)日：2008-10-14

    申请号：US11147506

    申请日：2005-06-07

    申请人： Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

    发明人： Yu-Ren Wang ,  Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Neng-Hui Yang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/6656 ,  H01L29/66666

    摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

    摘要翻译： 提供一种制造MOS晶体管的方法。 提供其上具有栅极结构的衬底。 在栅极结构的侧壁上形成第一间隔物。 进行预非晶化注入以使基板的一部分非晶化。 在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。 第二间隔件形成在第一间隔件的侧壁上。 在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。 此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。 最后，执行后退火操作。

    SiGe MOSFET with an erosion preventing Six1Gey1 layer
    8.
    发明授权
    SiGe MOSFET with an erosion preventing Six1Gey1 layer 有权
    SiGe MOSFET具有防腐蚀Six1Gey1层

    公开(公告)号：US07176504B1

    公开(公告)日：2007-02-13

    申请号：US11162904

    申请日：2005-09-28

    申请人： Huan-Shun Lin ,  Hung-Lin Shih ,  Hsiang-Ying Wang ,  Jih-Shun Chiang ,  Min-Chi Fan

    发明人： Huan-Shun Lin ,  Hung-Lin Shih ,  Hsiang-Ying Wang ,  Jih-Shun Chiang ,  Min-Chi Fan

    IPC分类号： H01L31/00

    CPC分类号： H01L29/165 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/665 ,  H01L29/66628

    摘要： A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer is deposited on the sidewalls of the gate structure. The SixGey layer is deposited in the substrate on both sides of the spacer and extended to a portion beneath part of the spacer. In addition, the top level of the SixGey layer is higher than the surface of the substrate. Moreover, the SixGey protection layer is deposited on the SixGey layer and the SixGey protection layer comprises Six1Gey1, where 0≦y1

    摘要翻译： 提供半导体器件。 该半导体器件包括衬底，栅极结构，间隔物，Si x Si x Ge层和Si x x Ge y y 保护层。 栅极结构沉积在衬底上，并且衬垫沉积在栅极结构的侧壁上。 Si衬底层沉积在间隔物的两侧的衬底中并延伸到间隔物部分下方的一部分。 此外，Si x Si层的顶层高于衬底的表面。 此外，Si Ge> y> protection protection protection is is <<<<<<<<<<<<<<<<<<<<<<<<<<< 其中0 <= y1 ，其中0≤y1≤y≤1。

    MOS transistor having reduced source/drain extension sheet resistance
    9.
    发明授权
    MOS transistor having reduced source/drain extension sheet resistance 有权
    MOS晶体管具有减少的源极/漏极延伸片电阻

    公开(公告)号：US06815770B1

    公开(公告)日：2004-11-09

    申请号：US10604741

    申请日：2003-08-14

    申请人： Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Yu-Kun Chen ,  Neng-Hui Yang

    发明人： Chin-Cheng Chien ,  Hsiang-Ying Wang ,  Yu-Kun Chen ,  Neng-Hui Yang

    IPC分类号： H01L2978

    CPC分类号： H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

    摘要： The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each sidewall of the gate electrode. A lightly doped source/drain extension is formed under the spacer with a raised epitaxial layer interposed between the spacer and the semiconductor substrate. The epitaxial layer, which is part of the lightly doped source/drain extension, has a lattice constant that is greater than the lattice constant of silicon crystal. The epitaxial layer serves as a solubility enhancement layer that is capable of increasing active boron concentration, thereby reducing sheet resistance of the source/drain extension. A heavily doped source/drain region is formed in the semiconductor substrate next to the edge of the spacer. A raised silicide layer is formed on the heavily doped source/drain region.

    摘要翻译： 本发明提供了一种新型的MOS晶体管结构。 MOS晶体管包括形成在半导体衬底上的栅电极和形成在栅电极和半导体衬底之间的栅氧化层。 在栅电极的每个侧壁上形成间隔物。 在间隔物之下形成轻掺杂的源极/漏极延伸部，其中插入在间隔物和半导体衬底之间的凸起的外延层。 作为轻掺杂源极/漏极延伸部分的外延层具有大于硅晶体的晶格常数的晶格常数。 外延层用作能够增加活性硼浓度，从而降低源极/漏极延伸部的薄层电阻的溶解度增强层。 在半导体衬底中，在间隔物的边缘附近形成重掺杂的源/漏区。 在重掺杂的源极/漏极区域上形成凸起的硅化物层。

    Method for fabricating metal-oxide semiconductor transistors
    10.
    发明授权
    Method for fabricating metal-oxide semiconductor transistors 有权
    金属氧化物半导体晶体管的制造方法

    公开(公告)号：US08053847B2

    公开(公告)日：2011-11-08

    申请号：US12324896

    申请日：2008-11-28

    申请人： Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

    发明人： Tsai-Fu Hsiao ,  Ching-I Li ,  Po-Yuan Chen ,  Chun-An Lin ,  Hsiang-Ying Wang ,  Chao-Chun Chen ,  Chin-Cheng Chien

    IPC分类号： H01L21/02

    CPC分类号： H01L21/324 ,  H01L21/265 ,  H01L21/2652 ,  H01L29/6659

    摘要： A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.

    摘要翻译： 公开了一种制造金属氧化物半导体晶体管的方法。 首先，提供其上具有栅极结构的半导体衬底，并且在栅极结构周围形成间隔物。 进行离子注入工艺以在分隔体的两侧将含有碳，硼和氢的分子簇注入到半导体衬底中，以形成掺杂区域。 分子簇的分子量优选大于100.此后，进行毫秒退火处理以激活掺杂区域内的分子簇。