公开(公告)号：US07601993B2

公开(公告)日：2009-10-13

申请号：US11636430

申请日：2006-12-11

申请人： Shinichi Hoshi ,  Masanori Itoh

发明人： Shinichi Hoshi ,  Masanori Itoh

IPC分类号： H01L31/072

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462

摘要： The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced.

摘要翻译： 本发明提供一种具有凹陷结构的欧姆电极的半导体器件，其中电阻小，并且由制造不规则性引起的电阻值的变化小。 在本发明的半导体器件中，通过从肖特基层提供的电子，在沟道形成层和肖特基层之间的界面上形成二维电子气层。 欧姆电极包括与二维电子气体层欧姆接触的多个侧面。 欧姆电极的至少一部分侧面不平行于沟道宽度方向。 在本发明的优选实施例中，侧面具有锯齿形或梳齿形。 由于欧姆电极和二维电子气体层之间的接触面积增加，所以欧姆电阻降低。

公开(公告)号：US20080023727A1

公开(公告)日：2008-01-31

申请号：US11878374

申请日：2007-07-24

申请人： Shinichi Hoshi ,  Masanori Itoh

发明人： Shinichi Hoshi ,  Masanori Itoh

IPC分类号： H01L31/072

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316

摘要： Deterioration of the high frequency characteristics of a field effect transistor is prevented, and the on- and off-gate leakage currents are reduced. A field effect transistor comprises the fourth electrode 126 between the gate electrode 122 and the drain electrode 118. The fourth electrode is formed to satisfy the relationship of 0.25=(FP2−D)/Lgd=0.5, where Lgd represents a distance between the gate and drain electrodes and FP2−D does the distance between the drain and fourth electrodes.

摘要翻译： 防止了场效应晶体管的高频特性的劣化，并且降低了栅极和栅极之间的漏电流。 场效应晶体管包括在栅电极122和漏电极118之间的第四电极126.第四电极形成为满足0.25 =（FP2-D）/Lgd=0.5的关系，其中Lgd表示栅极 并且漏电极和FP2-D确定漏极和第四电极之间的距离。

公开(公告)号：US20080283844A1

公开(公告)日：2008-11-20

申请号：US12149823

申请日：2008-05-08

申请人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

发明人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

IPC分类号： H01L29/778 ,  H01L21/338

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787

摘要： An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.

摘要翻译： 用于形成栅电极的开口由形成在绝缘膜上的第一光致抗蚀剂图案提供。 通过电感耦合等离子体的反应离子蚀刻通过第一光致抗蚀剂图案作为掩模施加到绝缘膜，从而暴露GaN半导体层的表面，在其上蒸发诸如NiAu的栅极金属，由此通过自对准形成栅极电极 处理。 这防止在半导体层的表面上形成氧化膜。 在形成栅电极之后，形成第二光致抗蚀剂图案，以通过第二光致抗蚀剂图案作为掩模在栅电极和绝缘膜上形成场板。 由此，可以使用与由SiN等制成的绝缘膜具有高粘接性的Ti作为场板金属。

公开(公告)号：US20080272443A1

公开(公告)日：2008-11-06

申请号：US12149325

申请日：2008-04-30

申请人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

发明人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

IPC分类号： H01L29/78 ,  H01L29/778

CPC分类号： H01L29/402 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/812

摘要： A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies.

摘要翻译： 场效应晶体管包括形成在半导体衬底上的有源层，在有源层上彼此分开形成的源极和漏极，形成在源极和漏极之间的栅极，形成在有源层上的第一层间膜， 第一场板（FP）电极，连接到栅电极并设置在栅极和漏极之间的第一层间膜上，形成在第一层间膜上的第二层间膜和连接到源极的第二FP电极， 在第一FP和漏电极之间的第二层间膜。 提供了在高频下表现出较高增益系数的场效应晶体管。

公开(公告)号：US20090315122A1

公开(公告)日：2009-12-24

申请号：US12549860

申请日：2009-08-28

申请人： Shinichi Hoshi ,  Masanori Itoh

发明人： Shinichi Hoshi ,  Masanori Itoh

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462

摘要： The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced.

摘要翻译： 本发明提供一种具有凹陷结构的欧姆电极的半导体器件，其中电阻小，并且由制造不规则性引起的电阻值的变化小。 在本发明的半导体器件中，通过从肖特基层提供的电子，在沟道形成层和肖特基层之间的界面上形成二维电子气层。 欧姆电极包括与二维电子气体层欧姆接触的多个侧面。 欧姆电极的至少一部分侧面不平行于沟道宽度方向。 在本发明的优选实施例中，侧面具有锯齿形或梳齿形。 由于欧姆电极和二维电子气体层之间的接触面积增加，所以欧姆电阻降低。

公开(公告)号：US07811872B2

公开(公告)日：2010-10-12

申请号：US12149823

申请日：2008-05-08

申请人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

发明人： Shinichi Hoshi ,  Masanori Itoh ,  Hideyuki Okita ,  Toshiharu Marui

IPC分类号： H01L21/338

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787

摘要： An opening for forming a gate electrode is provided by a first photoresist pattern formed on an insulating film. Reactive ion etching by inductively coupled plasma is applied to the insulating film through the first photoresist pattern as a mask to thereby expose the surface of a GaN semiconductor layer, evaporating thereon a gate metal such as NiAu, thereby forming the gate electrode by self-aligned process. This prevents an oxidized film from being formed on the surface of the semiconductor layer. After the gate electrode is formed, a second photoresist pattern is formed to form a field plate on the gate electrode and the insulating film through the second photoresist pattern as a mask. Thereby, Ti having a high adhesiveness with an insulating film made of SiN or the like can be used as a field plate metal.

摘要翻译： 用于形成栅电极的开口由形成在绝缘膜上的第一光致抗蚀剂图案提供。 通过电感耦合等离子体的反应离子蚀刻通过第一光致抗蚀剂图案作为掩模施加到绝缘膜，从而暴露GaN半导体层的表面，在其上蒸发诸如NiAu的栅极金属，由此通过自对准形成栅极电极 处理。 这防止在半导体层的表面上形成氧化膜。 在形成栅电极之后，形成第二光致抗蚀剂图案，以通过第二光致抗蚀剂图案作为掩模在栅电极和绝缘膜上形成场板。 由此，可以使用与由SiN等制成的绝缘膜具有高粘接性的Ti作为场板金属。

公开(公告)号：US20070132037A1

公开(公告)日：2007-06-14

申请号：US11636430

申请日：2006-12-11

申请人： Shinichi Hoshi ,  Masanori Itoh

发明人： Shinichi Hoshi ,  Masanori Itoh

IPC分类号： H01L29/76

CPC分类号： H01L29/7787 ,  H01L21/28587 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66462

摘要： The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced.

摘要翻译： 本发明提供一种具有凹陷结构的欧姆电极的半导体器件，其中电阻小，并且由制造不规则性引起的电阻值的变化小。 在本发明的半导体器件中，通过从肖特基层提供的电子，在沟道形成层和肖特基层之间的界面上形成二维电子气层。 欧姆电极包括与二维电子气体层欧姆接触的多个侧面。 欧姆电极的至少一部分侧面不平行于沟道宽度方向。 在本发明的优选实施例中，侧面具有锯齿形或梳齿形。 由于欧姆电极和二维电子气体层之间的接触面积增加，所以欧姆电阻降低。

公开(公告)号：US08598370B2

公开(公告)日：2013-12-03

申请号：US13380205

申请日：2010-06-29

申请人： Toshikazu Yagi ,  Koji Koyama ,  Masanori Itoh

发明人： Toshikazu Yagi ,  Koji Koyama ,  Masanori Itoh

IPC分类号： A61K31/4166 ,  C07D209/48

CPC分类号： C07D209/48 ,  C07C227/18 ,  C07C227/30 ,  C07C229/36

摘要： The present invention provides a process for producing Droxidopa or a pharmaceutically acceptable salt thereof comprising a step of reacting threo-N-phthaloyl-3-(3,4-dihydroxyphenyl)-L-serine represented by the formula (1) with methylamine, whereby a process for producing threo-3-(3,4-dihydroxyphenyl)-L-serine (common name: Droxidopa), which is useful as an agent for treatment of peripheral orthostatic hypotension or an agent for treatment of Parkinson's disease, with high production efficiency and without requiring troublesome operations.

摘要翻译： 本发明提供了一种制备Droxidopa或其药学上可接受的盐的方法，其包括使由式（1）表示的N-邻苯二甲酰基-3-（3,4-二羟基苯基）-L-丝氨酸与甲胺反应的步骤，由此 制备可用作治疗周围直立性低血压药物或治疗帕金森病药物的3-（3,4-二羟基苯基）-L-丝氨酸（通用名：Droxidopa）的方法，产量高 效率并且不需要麻烦的操作。

公开(公告)号：US08145041B2

公开(公告)日：2012-03-27

申请号：US11721604

申请日：2005-10-19

申请人： Hisataka Ueda ,  Hiroshi Yahata ,  Masanori Itoh ,  Hideaki Mita

发明人： Hisataka Ueda ,  Hiroshi Yahata ,  Masanori Itoh ,  Hideaki Mita

IPC分类号： H04N5/917

CPC分类号： G11B27/34 ,  G11B27/02 ,  G11B27/10 ,  G11B2220/90

摘要： A video processing device includes: encoder for generating a compressed video data by compressing and encoding a video data from camera unit; and system control unit for recording the compressed video data during a recording period from a recording start time to a recording end time as a video file and for recording, into recording memory, additional data as an index file that is information related to a compressed video data to be recorded in recording memory and, for reading the additional data together with the compressed video data from recording memory. System control unit records, into recording memory, the additional data recorded in the index file. The additional data is composed of additional data regarding the compressed video data recorded during the recording period and another additional data including a time code value showing a time at which a compressed video data to be recorded next is started.

摘要翻译： 视频处理装置包括：编码器，用于通过从相机单元压缩和编码视频数据来产生压缩视频数据; 以及系统控制单元，用于在从记录开始时间到记录结束时间的记录周期期间将压缩视频数据作为视频文件记录，并且将作为与压缩视频相关的信息的索引文件作为附加数据记录到记录存储器中 要记录在记录存储器中的数据，以及用于从记录存储器读取与压缩视频数据一起的附加数据。 系统控制单元将记录在索引文件中的附加数据记录到记录存储器中。 附加数据由关于在记录周期期间记录的压缩视频数据的附加数据组成，另外附加数据包括显示下一记录压缩视频数据开始的时间的时间码值。

公开(公告)号：US20110074012A1

公开(公告)日：2011-03-31

申请号：US12923579

申请日：2010-09-28

申请人： Masanori Itoh

发明人： Masanori Itoh

IPC分类号： H01L23/66

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L23/053 ,  H01L23/10 ,  H01L23/18 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/17135 ,  H01L2224/17164 ,  H01L2224/17517 ,  H01L2224/29007 ,  H01L2224/29013 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/8114 ,  H01L2224/81192 ,  H01L2224/83192 ,  H01L2224/922 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a substrate with a built-in semiconductor element, including: a first substrate at which a wiring layer is layered on a dielectric layer; a semiconductor element that is structured to include a distributed constant circuit, and at which plural bonding pads are formed at a peripheral region of a surface that faces the first substrate, and that is electrically connected to the wiring layer by an electrically-conductive member that has electrical conductivity and corresponds to the plural bonding pads; a supporting member that is disposed at an inner side region that is further toward an inner side than the peripheral region of the semiconductor element, and that is interposed between the semiconductor element and the first substrate and supports the semiconductor element; and a second substrate that is laminated to the first substrate and the semiconductor element.

摘要翻译： 提供了具有内置半导体元件的基板，包括：布线层在其上层叠在电介质层上的第一基板; 构造成包括分布常数电路的半导体元件，并且在面对第一基板的表面的周边区域形成有多个接合焊盘，并且通过导电构件电连接到布线层， 具有导电性并对应于多个键合焊盘; 支撑构件，其设置在比半导体元件的周边区域更靠内侧的内侧区域，并且设置在所述半导体元件和所述第一基板之间并支撑所述半导体元件; 以及层叠到第一基板和半导体元件的第二基板。